TCP/IP Segment Reordering via Hardware Parallel Comparison
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Solution Overview
Problem
Current software implementations of TCP/IP receiver logic are inefficient in handling high-speed network data, particularly in processing and reordering segments, due to serial execution and operating system performance constraints, leading to bottlenecks at network speeds above Gbps.
Innovation Solution
A hardware-based method for processing incoming TCP/IP segments involves parallel comparisons of sequence values to classify segments as in-order or out-of-order, using a processor to map results to dispositions, allowing for efficient reordering and saving or discarding segments, with operations completed within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software implementations of TCP/IP receiver logic are used, then ease of operation and adaptability are maintained, but processing speed and productivity deteriorate at high network speeds
Solution Approach 1:
The patent replaces software-based TCP/IP receiver logic with a hardware implementation that performs parallel comparisons of sequence values. This substitution of mechanical/system approach enables processing at line speed by utilizing hardware circuits instead of software execution, directly resolving the speed limitation at high network throughput.
Solution Approach 2:
The hardware implementation segments the TCP/IP processing function into distinct parallel comparison units that evaluate sequence values independently. Each unit can compare sequence numbers simultaneously, dividing the overall processing task into concurrent operations that collectively achieve high-speed segment reordering without software bottlenecks.
2Productivity
If serial execution in software is used, then device complexity is reduced, but processing time and productivity worsen
Solution Approach 1:
The hardware implementation employs periodic clock cycles to drive simultaneous comparison operations across multiple sequence value pairs. Each clock cycle represents a periodic action where all comparison units operate in unison, processing multiple segments in parallel rather than sequentially, thereby dramatically reducing total processing time.
Solution Approach 2:
The system performs preliminary classification of segments as in-order or out-of-order through parallel comparison against previously received segments. This preliminary action occurs in hardware before software handling is needed, pre-processing the reordering logic and enabling faster overall throughput by eliminating sequential software-based reordering delays.
3Power
If operating system constraints are applied, then ease of operation is maintained, but processing speed and power efficiency deteriorate
Solution Approach 1:
The hardware implementation performs TCP/IP receiver functions autonomously without requiring operating system intervention for each segment processing operation. The system serves itself by maintaining internal state (previous segment sequence values) and performing comparisons independently, eliminating OS context switching and memory management overhead that consume processor power and time.
Data Source
AI summary
A method for a receiver to perform processing of incoming data segments transmitted over a network by a transmitter in accordance with a transport protocol. The segments incorporate sequence values indicative of a transmission order of the segments. The method consists of receiving the data segments over the network in a reception order. Then, for each segment received in the reception order, the sequence values of the received segment and of the segments received earlier in the reception order are compared in order to assign the received segment a classification identity as an in-order or out-of-order segment.The method further includes writing the segments, in a writing order that is substantially identical to the reception order, to respective locations in an output buffer responsive to the classification identity of each segment, so that the segments in the output buffer are arranged in the transmission order.