Multi-Core TCP Session Processing Architecture
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Solution Overview
Problem
Existing methods for conducting TCP sessions during network testing are inefficient as they utilize a single processor core, even when multiple CPU cores are available, leading to reduced performance and scalability as network transmission rates increase.
Innovation Solution
A novel TCP session processing architecture that distributes TCP session processing across multiple processor cores, with shared memory and atomic spinlock instructions to manage protocol control blocks, allowing concurrent handling of TCP sessions by separate cores for control, transmission, and receipt.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single processor core is used for TCP session processing, then the system is simple to implement, but the performance and scalability are limited as network transmission rates increase
Solution Approach 1:
The patent divides the TCP session processing into separate functional segments handled by different processor cores: control plane processing (connection establishment, state management) is separated from data plane processing (packet transmission and reception). This segmentation allows each core to specialize in specific tasks, improving overall system throughput and scalability while maintaining manageable complexity through clear functional separation.
Solution Approach 2:
The patent transitions from single-core sequential processing to multi-core parallel processing by adding a new dimensional aspect of concurrency. Multiple processor cores are introduced to handle TCP sessions simultaneously, with shared memory providing a common space for protocol control blocks. This dimensional expansion from 1D (single-core) to multi-dimensional (multi-core) processing significantly increases productivity without proportionally increasing implementation complexity.
2Adaptability or versatility
If multiple processor cores are used for TCP session processing, then the scalability and handling capacity increase, but the system complexity increases
Solution Approach 1:
The patent creates a universal shared memory space that serves multiple functions: storing protocol control blocks for connection state management, providing common access for both control plane and data plane processors, and enabling coordinated operation across all processor cores. This universal data structure simplifies the multi-core architecture by providing a single source of truth for all cores, reducing the complexity that would otherwise arise from multiple separate data structures and inter-core communication mechanisms.
Solution Approach 2:
The shared memory acts as an intermediary between the different processor cores, providing a common communication and coordination medium. Instead of requiring complex inter-process communication mechanisms or shared memory segmentation, the patent uses a unified shared memory space that automatically provides both data storage and inter-core communication functions, thereby reducing architectural complexity while enabling high scalability.
3Productivity
If TCP sessions are processed sequentially on a single core, then the state management is straightforward, but the number of concurrent sessions is limited
Solution Approach 1:
The patent segments the state management by creating separate protocol control blocks for each TCP connection, with each block independently managed by the appropriate processor core. This segmentation allows multiple concurrent sessions to be processed in parallel without state interference, as each connection maintains its own isolated state structure. The control plane and data plane also maintain separate state management responsibilities, further dividing complexity across multiple cores.
Data Source
AI summary
The disclosed technology teaches TCP session processing architecture for conducting numerous TCP sessions during testing of a network-under-test: multiple processor cores running, allocated to TCP session handling, and program instructions configured to distribute processing of each TCP session across multiple cores with a first set of cores allocated to handle TCP control, a second set of cores allocated to handle TCP packet transmission, and a third set of cores allocated to handle TCP packet receiving. The disclosed architecture also includes a shared memory accessible to the first, second and third sets of cores, that holds PCBs for each of numerous TCP sessions during the testing with update access controlled by an atomic spinlock processor instruction that each TCP state machine running on a core must engage to secure the update access to a respective PCB, in order to proceed with state processing of its respective TCP session.