Carrier Substrate TCV Layout for Dense Die Packaging Heat Paths
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller, more efficient packaging techniques for semiconductor dies due to limitations in miniaturization, higher speed, greater bandwidth, and enhanced thermal spreading capabilities, which existing technologies have not adequately addressed.
Innovation Solution
The development of a carrier substrate with through carrier vias (TCVs) embedded in an insulating body, where the TCVs are formed using an electro-plating process to ensure high electrical conductivity and quality, allowing for efficient electrical connection and thermal management, and potentially reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but miniaturization and thermal spreading capability are insufficient
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional vertical stacking architecture. Multiple semiconductor dies are stacked vertically with intermediate carrier substrates, enabling miniaturization by utilizing the vertical dimension rather than expanding horizontally. This dimensional change allows higher integration density while maintaining manageable complexity through modular layering.
Solution Approach 2:
The packaging structure is divided into multiple discrete layers including semiconductor dies, intermediate carrier substrates, and encapsulants. Each layer performs specific functions and can be manufactured and tested independently before assembly. This segmentation enables miniaturization of individual components while the overall system achieves high integration through vertical stacking.
2Quantity of substance
If feature size is reduced to increase integration density, then more components fit in given area, but thermal spreading capability deteriorates
Solution Approach 1:
The patent addresses thermal management by transitioning from two-dimensional heat dissipation to three-dimensional thermal pathways. Heat generated by densely packed components is conducted vertically through intermediate carrier substrates with embedded heat dissipation structures, spreading thermal energy across multiple layers and improving overall thermal management capability despite high integration density.
3Reliability
If electro-plating process is used for TCVs, then electrical conductivity and quality are improved, but manufacturing complexity increases
Solution Approach 1:
The electro-plating process for forming through carrier vias (TCVs) is performed as a preliminary step during intermediate carrier substrate fabrication, before final assembly. This preliminary action ensures high electrical conductivity of interlayer connections is established early in the manufacturing process, and the TCVs serve as pre-formed conductive pathways that simplify subsequent assembly steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of smaller, more efficient package structures with improved electrical connectivity and thermal management, reducing manufacturing costs and enhancing the quality of semiconductor packages.
Implementation Method 1
the TCVs are formed using an electro-plating process to ensure high electrical conductivity and quality
Data Source
AI summary
A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.