TD-SCDMA Timing Control via Single TAS Signal
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Solution Overview
Problem
Current timing control sequences for TD-SCDMA and LTE-TDD mobile terminals are complex and provide only coarse timing references, making precise timing adjustments for all transmit slots challenging.
Innovation Solution
A timing control system that includes a radio frequency integrated circuit (RFIC), a baseband integrated circuit (BBIC), a first-in first-out (FIFO) buffer, and a modulo counter, which uses a single time accurate strobe (TAS) signal to calculate and store timing adjust values for each frame time slot, allowing for precise timing adjustments without additional control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complex control sequence is used over the asynchronous serial interface, then coarse timing references can be provided, but precise timing control for all TX slots cannot be achieved
Solution Approach 1:
The system pre-calculates and stores timing adjustment values for all subsequent frame time slots in advance. When a timing correction is received, the BBIC calculates the adjustment values for all future slots and stores them in the memory, eliminating the need for complex real-time control sequences and enabling precise timing without additional control signals.
Solution Approach 2:
The invention creates a simplified copy of the timing control mechanism by using a single TX TAS signal to trigger pre-calculated timing adjustments. Instead of using complex control sequences for each slot, the system uses a single control signal that references pre-computed timing values, dramatically reducing interface complexity while maintaining precision.
2Measurement precision
If additional control signals are issued for each frame time slot, then precise timing can be achieved, but the control sequence complexity increases
Solution Approach 1:
The invention merges multiple timing control operations into a single TX TAS signal event. By pre-calculating all timing adjustments and storing them in memory, the system combines what would otherwise require multiple separate control signals into one triggering event, reducing complexity while maintaining precise timing control for all frame time slots.
3Measurement precision
If timing adjustments are calculated in real-time, then precise timing can be provided, but processing delays increase
Solution Approach 1:
The system performs timing adjustment calculations in advance and stores the results in memory. When a timing correction is received, the BBIC immediately retrieves pre-calculated values from memory rather than computing them in real-time, eliminating processing delays while maintaining precise timing control for all subsequent frame time slots.
Data Source
AI summary
A timing control system includes a counter that is initiated by a time accurate strobe (TAS) signal. A counter value is recorded when a message arrives in a buffer. A baseband integrated circuit (BBIC) calculates an integer number of counter periods and a fraction of a counter period corresponding to a timing correction value received from a base station. The BBIC issues a TAS signal during a counter period that occurs at the integer number of counter periods. At an expiration of the fraction of an ensuing counter period, the first one of a plurality of frame time slots is sent from the buffer to an antenna via a radio frequency integrated circuit (RFIC). The BBIC calculates, then stores in a memory, timing adjust values for the plurality of frame time slots so that each frame time slot can be time adjusted during message transmissions without an issuance of an additional TAS signal.