TD-SCDMA TTI Memory Structure for Asymmetric Traffic Handling
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Solution Overview
Problem
TD-SCDMA uplink processing systems face challenges in efficiently managing asymmetric traffic and bandwidth requirements due to the lack of dynamic adjustment mechanisms for time slots, leading to inefficiencies in data transmission.
Innovation Solution
Implementing a wireless communication device with a TTI memory structure that allows for padding of bits without calculating the number of padded bits, enabling equal-sized segments for radio frame equalization, and sharing a dual-port frame memory among bit rate, chip rate processors, and DSP software to simplify hardware design and improve flexibility in configuring chip rate processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic adjustment mechanisms for time slots are implemented, then flexibility in handling asymmetric traffic is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic adjustment mechanisms that allow the system to adapt time slot configurations based on asymmetric traffic requirements. The mechanism dynamically modifies transmission parameters without requiring complex manual reconfiguration, enabling flexible handling of varying uplink and downlink traffic patterns while maintaining manageable system complexity through automated control.
2Manufacturing precision
If calculation of padded bits is performed, then precision in memory alignment is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary calculations to determine the number of padded bits required for memory alignment before the actual data processing begins. By pre-calculating the padding requirements based on the relationship between transport block size, code block size, and memory line structure, the system achieves precise memory alignment without adding significant processing time during critical data transmission operations.
3Reliability
If separate memory structures are used for different processing stages, then data integrity is improved, but hardware complexity increases
Solution Approach 1:
The patent employs a universal memory structure that serves multiple processing stages including transport channel encoding, code block segmentation, and rate matching. By designing the memory to handle different data formats and processing requirements through a unified architecture with configurable parameters, the system maintains data integrity across processing stages while avoiding the hardware complexity of completely separate memory structures for each stage.
Data Source
AI summary
A wireless system includes a TTI memory architecture in which encoded data are stored in a memory at a rate of one block of encoded data per transmission time interval (TTI), TTI being selected from a set of predetermined values, the memory including memory lines each having a predetermined number of bits that is determined according to the set of predetermined TTI values. For every block of data in which the end of the block of data does not align with an end of a last memory line occupied by the block of data, one or more padded bits are stored after the end of the block of data to the end of the last memory line occupied by the block of data so the last memory line is filled with a portion of the block of data and the one or more padded bits. The block of data and the padded bits are read in one or more equal sized segments.