TDC AD Conversion Circuit for Accurate Lower Phase Encoding
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Solution Overview
Problem
The existing time-to-digital converter (TDC) type AD conversion circuits with asymmetric oscillation circuits face errors in lower data due to simultaneous changes in lower phase signals, leading to incorrect encoding of logic states and resulting in precision issues during analog-to-digital conversion.
Innovation Solution
The proposed AD conversion circuit includes a reference signal generation unit, a comparison unit, a clock generation unit with an oscillation circuit having an odd number of delay units, a latch unit, and an encoding unit that detects and encodes logic states of multiple lower phase signals in a predetermined order, ensuring accurate state detection and encoding based on the timing of signal changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an asymmetric oscillation circuit is used in the TDC type AD conversion circuit, then the conversion speed is improved, but errors occur in lower data due to simultaneous changes in lower phase signals
Solution Approach 1:
The patent applies preliminary action by detecting the simultaneous change of lower phase signals before the encoding process occurs. The detection circuit monitors the lower phase signals and identifies when they change simultaneously, then prevents erroneous encoding from occurring by blocking the encoding operation at that moment. This proactive approach resolves the contradiction by maintaining both high conversion speed and accurate lower data precision.
2Productivity
If the encoding circuit encodes logic states based on lower phase signals, then the AD conversion is completed, but incorrect encoding occurs when lower phase signals change simultaneously
Solution Approach 1:
The patent implements feedback by having the detection circuit continuously monitor the lower phase signals and provide feedback information to the encoding circuit. When simultaneous changes are detected, the feedback signal prevents incorrect encoding. This closed-loop control ensures that encoding only occurs when conditions are appropriate, maintaining both productivity and reliability.
3Stability of the object's composition
If a ring delay circuit with odd number of delay units is used, then the oscillation stability is improved, but the circuit complexity increases
Solution Approach 1:
The patent applies parameter changes by specifically selecting an odd number of delay units (n ≥ 3) in the ring delay circuit. This parameter choice ensures that the oscillation circuit produces stable lower phase signals with predictable timing relationships. The odd number configuration creates a specific phase distribution that prevents simultaneous changes in all lower phase signals, thereby achieving oscillation stability while keeping the circuit design systematic and manageable.
Data Source
AI summary
An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.