Time-to-digital converter asynchronous reset for time-domain bias
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Solution Overview
Problem
Time-domain bias in time-to-digital converters (TDCs) occurs due to their fixed measurement periods, leading to missed events when event frequencies are high, and inefficient event recording when multiple single-photon avalanche diodes (SPADs) are used, resulting in a non-uniform distribution of recorded events over time.
Innovation Solution
The input stage of the TDC is asynchronously reset using a delay line, allowing events to be uniformly distributed by blocking the input stage for a time interval of independent duration, which is selected in advance and can vary within a specified range, ensuring that the probability of event latching is consistent across measurement periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a fixed measurement period is used in the TDC, then the device can operate with simple control logic, but events occurring after the first event in each period are missed, causing time-domain bias
Solution Approach 1:
The patent applies dynamics by making the measurement period asynchronous and adaptive. Instead of a fixed synchronous period, the system dynamically adjusts the measurement window based on when events occur. The second event in each asynchronous period becomes the new reference point, allowing the measurement period to shift and extend indefinitely, thus capturing all events without bias while maintaining simple control logic.
2Area of stationary object
If multiple SPADs are connected to a single TDC to extend sensing area, then the detection area increases, but the probability of missing subsequent events increases drastically
Solution Approach 1:
The patent resolves this contradiction by making the measurement period dynamic and asynchronous. When multiple SPADs are used, the system doesn't rely on fixed synchronous periods that cause bias. Instead, each event triggers a new asynchronous measurement period, ensuring that regardless of which SPAD detects an event, the system captures it accurately without missing subsequent events from other SPADs.
Solution Approach 2:
The patent changes the parameter of measurement period from fixed and synchronous to variable and asynchronous. This parameter change allows the system to adapt to different event arrival times from multiple SPADs, maintaining accurate event recording while extending the sensing area through multiple photodetectors.
3Device complexity
If the TDC resets according to fixed measurement periods, then the control is simplified, but a non-uniform distribution of recorded events occurs over time
Solution Approach 1:
The patent applies dynamics by transitioning from fixed synchronous reset to asynchronous reset based on actual event occurrence. The measurement period is no longer a static parameter but dynamically adjusts to start from the second event in each period. This dynamic approach eliminates time-domain bias and produces uniform event distribution while keeping control logic simple.
Solution Approach 2:
The patent implements feedback by using the actual occurrence of events to trigger and reset the measurement period. The second event in each period feeds back to become the new reference point, creating a self-adjusting system that automatically compensates for timing variations and ensures uniform event distribution without complex external control.
Data Source
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AI summary
The method comprises providing a time-to-digital converter with a measurement period (3) for registration of events (1), and selecting time intervals of independent durations (4), each of the durations being independent of the registration of events. At each registration of an event, the time-to-digital converter is blocked from further registration for one of the time intervals of independent duration. Thus the recorded lengths of the time intervals (11, 13, 14, 16) corresponding to the occurrence of the events within each measurement period are uniformly distributed and a time-domain bias is avoided. The time-to-digital converter circuit includes a controlled gate for blocking the time-to-digital converter.