TDC Calibration in ADPLLs Without Extra Compensation Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
All-digital phase-locked loops (ADPLLs) require precise calibration of time-to-digital converter (TDC) gain and nonlinearity to ensure optimal performance, but existing methods often add extra detection and compensation circuits, increasing circuit area and power consumption.
Innovation Solution
A method and apparatus for estimating and calibrating TDC mismatches by capturing phase error or output code samples, generating accumulation values, calculating differences, and adjusting the correction gain to reduce TDC normalizing gain and nonlinearity errors, using existing ADPLL circuitry to save resources and improve accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extra detection and compensation circuits are added to calibrate TDC gain and nonlinearity, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the TDC calibration function with the existing phase error detection circuitry in the ADPLL. The phase error samples that already exist in the system are reused for calibration purposes, merging two functions (phase error detection and TDC calibration) into a single integrated process, thereby avoiding additional dedicated calibration circuits
Solution Approach 2:
The patent makes the existing phase error detection circuitry serve dual purposes: its original function of detecting phase errors for PLL control and an additional function of providing calibration data for TDC gain and nonlinearity correction. This multi-functionality eliminates the need for separate calibration detection circuits
2Measurement precision
If traditional calibration methods are used to improve TDC performance, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The calibration process merges with the normal ADPLL operation by using the same phase error samples and control voltage that already exist during phase locking. This integration allows calibration to occur without activating separate high-power calibration circuits, thereby reducing overall power consumption
Solution Approach 2:
The system performs self-calibration by using its own operational data (phase error samples and control voltages) to detect and correct TDC nonlinearity. This self-service approach eliminates the need for external calibration equipment or additional calibration circuits that would consume extra power
Data Source
AI summary
A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.