High-Resolution TDC Calibration for ADPLL Phase Alignment
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Solution Overview
Problem
All Digital Phase Locked Loops (ADPLLs) face challenges in achieving fine resolution in Time to Digital Converters (TDCs), leading to quantization errors and performance issues due to finite resolution, particularly in applications requiring stringent phase noise reduction like radar systems.
Innovation Solution
A medium-fine based TDC topology is implemented, comprising a medium resolution delay unit and a fine resolution delay unit with capacitors in series, utilizing a calibration method that adjusts the calibration delay value to align the outputs of the delay banks, and employing a fast flip flop to determine phase alignment, allowing for incremental delay adjustments to achieve precise calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC topology is used in ADPLL, then the device complexity is reduced, but the measurement precision of time delay is insufficient leading to quantization errors
Solution Approach 1:
The TDC is segmented into multiple delay banks (first delay bank and second delay bank) with different resolution levels. The medium resolution delay unit provides coarse timing while the fine resolution delay unit provides precise timing, allowing the system to achieve high measurement precision without requiring a single complex high-resolution delay structure throughout.
Solution Approach 2:
Different regions of the delay structure are assigned different quality levels. The fine resolution delay unit uses capacitors in series to achieve sub-picosecond resolution locally, while the medium resolution delay unit handles broader timing ranges. This local optimization of delay precision resolves the contradiction by providing high measurement precision only where needed in the timing measurement process.
2Measurement precision
If fine resolution delay unit with capacitors in series is used, then the measurement precision is improved, but the device complexity increases due to multiple delay banks and calibration requirements
Solution Approach 1:
A calibration process is performed before normal operation to pre-align the medium resolution delay unit and fine resolution delay unit. The calibration delay value is determined by comparing outputs from both delay banks and adjusting the fine resolution unit accordingly. This preliminary action eliminates the need for complex real-time coordination between delay banks during operation, reducing the effective complexity of the system.
Solution Approach 2:
The system uses feedback from the fast flip flop output to determine whether the delay units are properly aligned. The fast flip flop compares timing signals from both delay banks and provides feedback that drives the calibration process, automatically adjusting the fine resolution delay unit until alignment is achieved. This feedback mechanism simplifies the control complexity by using self-correcting timing comparison rather than complex external control logic.
3Measurement precision
If calibration process is implemented to align delay banks, then the measurement precision is improved, but the loss of time occurs during calibration and re-calibration
Solution Approach 1:
The calibration process is performed as a preliminary action during system initialization or startup, establishing the correct alignment between delay banks before normal measurement operations begin. Once calibrated, the system maintains this alignment during normal operation without requiring frequent re-calibration, thus minimizing the time penalty to a single initial calibration event rather than continuous time loss.
Solution Approach 2:
The calibration system uses the existing timing signals and delay structures to perform self-calibration without requiring external calibration equipment or complex external control. The fast flip flop and existing delay banks work together to automatically determine and apply the correct calibration delay value, reducing calibration time by eliminating the need for external intervention or complex calibration procedures.
Data Source
AI summary
Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.