Time-to-digital converter calibration using high-frequency reference clock
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Solution Overview
Problem
Conventional time-to-digital converter systems face challenges in accurately converting time intervals to digital outputs due to the dependence of bin addresses on oscillator frequency, which may be unknown or variable, leading to uncertainties in physical representations of time differences.
Innovation Solution
The implementation of a calibration clock signal with a frequency higher than the measurement clock signal by a predefined ratio, allowing multiple clock edges within the measurement interval, enables precise determination of time differences and bin addresses, thereby improving the accuracy of time-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional oscillator-driven TDC is used, then the device can convert time differences to digital values, but the bin address depends on oscillator frequency which may be unknown or variable, reducing measurement precision
Solution Approach 1:
A calibration clock signal is introduced as an intermediary reference with a known, stable frequency relationship to the measurement clock signal. This calibration signal serves as a mediator that establishes a reliable reference framework, allowing the system to determine actual time measures for histogram bins even when the oscillator frequency varies or is unknown. The calibration signal bridges the gap between the variable oscillator output and the required precise time measurement.
2Measurement precision
If a calibration clock signal with higher frequency is used, then multiple clock edges fall within the measurement interval enabling precise time difference determination, but the device complexity increases
Solution Approach 1:
The system changes the frequency parameter of the calibration clock signal to be higher than the measurement clock signal by a predefined ratio. This parameter change ensures that multiple calibration clock edges fall within a single measurement interval, enabling more precise determination of time differences and histogram bin addresses. The higher frequency provides more reference points without requiring fundamental changes to the TDC architecture.
3Measurement precision
If the measurement clock signal frequency is used directly, then the measurement interval matches the TDC range, but offset effects cannot be eliminated, reducing measurement precision
Solution Approach 1:
The calibration clock signal is designed to operate at a higher frequency than the measurement clock signal, creating more calibration events than strictly necessary. This excessive action ensures that at least two (and potentially more) calibration clock edges fall within each measurement interval, providing multiple opportunities to measure and eliminate offset effects. The additional calibration points enable more robust differential measurements that cancel out systematic errors.
Solution Approach 2:
The calibration clock signal provides periodic reference edges at a higher frequency than the measurement signal. These periodic calibration events occur regularly throughout the measurement interval, enabling systematic elimination of offset effects through differential measurement of multiple clock edge pairs. The periodic nature ensures consistent reference points for calibration.
Data Source
AI summary
A time-to-digital converter system has at least one time-to-digital converter comprising an oscillator, a counter being driven by the oscillator, an evaluation block connected to the counter and configured for determining a time difference associated with a start signal and a stop signal, and a histogram block with a number of bins for recording entries associated with the time difference. The system can be calibrated by operating or preparing to operate the time-to-digital converter system with a measurement clock signal defining a measurement interval, providing a calibration clock signal having a frequency higher than the measurement clock signal by a predefined ratio, using a selected clock edge of the calibration clock signal as the start signal and a subsequent clock edge of the calibration clock signal as the stop signal. The evaluation block determines a calibration time difference based on the respective clock edges of the calibration clock signal used as the start signal and the stop signal. A time measure associated with a counter step of the counter is determined based on the predefined ratio and the calibration time difference.