Metastable Ring Oscillator TDC Calibration for Timing Accuracy
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Solution Overview
Problem
Time-to-digital converters (TDCs) in nuclear medicine imaging, particularly in time-of-flight PET systems, face accuracy challenges due to manufacturing variations in on-chip circuit speeds, leading to significant variations in delay chain steps, which affect timing accuracy and position estimation in positron emission events.
Innovation Solution
A metastable ring oscillator TDC with a programmable delay chain implemented on FPGAs, utilizing a signal generating circuit, carry elements, and delay modules with feedback lines and enable inputs to introduce and calibrate propagation delays, optimizing timing accuracy by adjusting the ring oscillator period to compensate for structural nonlinearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay chain TDC is used to measure timing, then timing measurement capability is provided, but manufacturing variations cause significant variations in delay steps affecting accuracy
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual timing operations. The system pre-determines optimal delay values for each chip by measuring actual delay steps and storing calibration data in lookup tables, so that when timing measurements are performed, the pre-calibrated values are used to compensate for manufacturing variations.
Solution Approach 2:
The patent changes the parameter of delay values dynamically based on calibration results. Instead of using fixed delay chain steps, the system adjusts delay parameters by selecting from multiple possible delay values stored in lookup tables, choosing the optimal value that compensates for the specific chip's manufacturing characteristics.
2Measurement precision
If coarse offsets are designed into the TDC to improve timing accuracy, then timing accuracy over single-edge delay chain is improved, but manufacturing variation in circuit speed still affects optimal delay selection
Solution Approach 1:
The patent extends parameter changes by providing multiple coarse offset values in the lookup table corresponding to different delay chain configurations. The calibration process determines which coarse offset value is optimal for each chip, and the system can switch between different offset parameters to adapt to manufacturing variations.
Solution Approach 2:
The patent implements feedback by using the calibration process to measure actual delay performance and use this information to select optimal operating parameters. The measured delay values feed back into the lookup table population, creating a closed-loop system that adapts to each chip's specific characteristics.
3Measurement precision
If multiple delay chains are used to reduce variation, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing all necessary calibration and optimization work before the TDC is used for actual timing measurements. The lookup tables are pre-populated with optimal values, so the runtime operation is simple and does not require complex real-time adjustments or multiple active delay chains.
Solution Approach 2:
The patent uses copying by creating lookup tables that contain pre-computed optimal delay values for different conditions. Instead of having multiple physical delay chains operating simultaneously, the system copies the essential information (optimal delay values) into lookup tables that can be quickly referenced during timing operations.
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AI summary
Timing accuracy of a TDC can be improved. An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The signal generating circuit is configured to generate a start signal. The plurality of carry elements are connected as a chain, and each of the carry elements has an input to receive a stop signal. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.