Time-to-Digital Converter Calibration Using a Virtual PLL
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Solution Overview
Problem
Time-to-digital converters in clock generators experience gain errors that increase noise and spurs in the output, due to mismatched gains between coarse and fine converters, which affects the accuracy of clock signals.
Innovation Solution
A calibration technique using a virtual phase-locked loop is implemented to generate a calibration signal that adjusts the gain of the fine time-to-digital converter to match the coarse converter's gain, reducing phase noise and spurs by averaging error signals over multiple clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a time-to-digital converter is used to generate clock signals, then the clock signals can be produced with flexible frequency, but gain errors in the converter increase noise and spurs in the output
Solution Approach 1:
The patent applies preliminary action by performing calibration of the time-to-digital converter before normal operation. The calibration process pre-determines correction values that compensate for gain errors, so that when the converter operates in normal mode, the accuracy issues are already resolved. This is evident in the calibration mode where the system measures and stores correction data that will be applied during subsequent clock signal generation.
Solution Approach 2:
The patent implements feedback by using the output of the time-to-digital converter to adjust its own operation. The calibration process feeds back correction information to the converter to minimize gain errors. The system continuously monitors the relationship between coarse and fine converter outputs and adjusts calibration parameters to reduce noise and spurs in the final output.
2Measurement precision
If gain calibration is performed to reduce noise and spurs, then output accuracy improves, but the device complexity increases due to additional calibration circuits
Solution Approach 1:
The patent merges the calibration functionality with the existing time-to-digital converter structure. Rather than adding completely separate calibration equipment, the calibration circuits are integrated into the converter itself, sharing common components such as the coarse and fine converters, phase detectors, and logic circuits. This reduces overall system complexity while still achieving accurate gain calibration.
Solution Approach 2:
The calibration circuits are designed to perform multiple functions: they can operate in calibration mode to measure and correct gain errors, and in normal operation mode to generate clock signals. The same hardware infrastructure supports both calibration and normal operation, making the system more efficient and less complex than having separate dedicated calibration equipment.
3Measurement precision
If averaging error signals over multiple clock cycles is performed, then noise and spurs are reduced, but the calibration time increases
Solution Approach 1:
The patent applies partial action by performing averaging over a limited number of clock cycles rather than indefinitely. The system determines an optimal averaging window that provides sufficient noise reduction without excessive calibration time. This balanced approach achieves acceptable error signal accuracy while maintaining reasonable calibration speed for practical applications.
Data Source
AI summary
A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.