TDC Charge-Current Control for Low-Power ADPLL Phase Detection

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Solution Overview

Problem

Conventional time-to-digital converters in phase locked loops face high power consumption and require calibration due to process, voltage, and temperature variations, especially when dealing with large phase differences between reference and DCO frequencies.

Innovation Solution

A time-to-digital converter with an analog-to-digital converter using a charge capacitor and a current source circuit that supplies a charge current with a constant gradient, eliminating the need for calibration and reducing power consumption by using a switched capacitor with a proportional charge current and matching switching frequency with phase detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional TDC with SS-ADC is used to detect large phase differences, then measurement precision is improved, but power consumption increases because the charge pump must operate continuously for several clock cycles

Engineering Contradiction:

Improvephase difference detection precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The charge pump operates periodically rather than continuously. The control signal enables the charge pump only during specific time windows corresponding to the reference clock cycle, allowing it to remain inactive during other periods. This periodic operation maintains the ability to measure large phase differences while significantly reducing average power consumption.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The hold capacitor stores the charge accumulated during the active period of the charge pump, preserving the phase difference information for the entire measurement cycle. This preliminary charging action during a brief window allows the system to handle large phase differences without requiring continuous charge pump operation.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the charge pump operates continuously to handle large phase differences, then reliability is improved, but power consumption increases

Engineering Contradiction:

Improvephase difference detection reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The charge pump is controlled by a periodic enable signal that synchronizes with the reference clock. This allows the charge pump to be activated only when needed (during the reference clock cycle) and remain inactive otherwise, maintaining reliable phase difference detection while reducing power consumption.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The hold capacitor automatically retains the charge information without requiring continuous active maintenance. The system uses the natural charge storage capability of the capacitor to maintain reliability during periods when the charge pump is inactive, eliminating the need for continuous operation.

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If inverter circuits are increased to handle large phase differences, then adaptability is improved, but device complexity increases

Engineering Contradiction:

Improverange of detectable phase differencesVSAvoidnumber of inverter circuits

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical approach of using multiple inverter circuits with an electrical approach using a charge pump and hold capacitor. The charge pump generates voltage proportional to the phase difference, and the capacitor stores this information, eliminating the need for complex cascaded inverter structures while maintaining the ability to handle large phase differences.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system changes the measurement parameter from direct digital counting (using inverter circuits) to analog voltage proportional to time/phase difference. By measuring the voltage on the hold capacitor rather than counting through multiple inverter stages, the system achieves wide adaptability with simpler circuitry.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively suppresses power consumption and eliminates the need for calibration, maintaining a constant dynamic range and generating accurate digital values despite PVT variations.

Implementation Method 1

an analog-to-digital converter including a predetermined charge capacitor; and a current source circuit configured to supply a charge current that charges the charge capacitor with a charge

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11251797B2Time-to-digital converter and phase locked loop

Publication Date: 2022.02.15 SONY SEMICON SOLUTIONS CORP

AI summary

Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.