TDC-Based Clock Delay Buffering for High Resolution and Large Range
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Solution Overview
Problem
Existing phase-locked loops (PLLs) face challenges in achieving both high resolution and large delay ranges, with analog delays providing high resolution but limited range, and digital delays offering large ranges but lacking precision.
Innovation Solution
Utilizing time-to-digital converters (TDCs) to sample clock edges and store digital values in memory, allowing for high-resolution delays with large ranges by queuing and dequeuing these values after a predetermined delay, ensuring accurate signal buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analog delays are used to delay input signals, then high resolution is achieved, but large delay ranges cannot be accommodated
Solution Approach 1:
The delay function is segmented into two independent components: an analog delay chain for high-resolution fine-tuning and a digital counter for large-range coarse adjustment. This segmentation allows each component to specialize in one aspect of the delay requirement without compromising the other.
Solution Approach 2:
The patent merges the analog delay chain and digital counter into a unified delay system where both components work together. The analog delay provides precise timing control while the digital counter extends the overall delay range, achieving both high resolution and large delay range simultaneously.
2Adaptability or versatility
If digital delays are used to delay input signals, then large delay ranges are achieved, but high resolution is lost
Solution Approach 1:
The delay function is segmented into two independent parts: a digital counter for large-range coarse delay and an analog delay chain for high-resolution fine-tuning. This allows the digital component to handle the range requirement while the analog component preserves precision.
Solution Approach 2:
The digital counter and analog delay chain are merged into a hybrid delay system where the digital counter establishes the base delay range and the analog delay chain adds precise fractional delay capability, combining the advantages of both approaches.
3Reliability
If PLL buffers input signals for quality analysis, then input quality can be evaluated, but signal delay is required
Solution Approach 1:
The hybrid delay system serves multiple functions: it provides the required signal buffering for quality analysis while simultaneously offering programmable delay control and high-resolution timing. This multi-functionality reduces the need for separate dedicated buffering circuits.
Solution Approach 2:
The system allows dynamic adjustment of delay parameters through digital control, enabling flexible buffering durations adapted to different quality analysis requirements without redesigning the buffering architecture.
Data Source
AI summary
A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.