TDC-Based Clock Delay for High Resolution and Large Range

Solution Overview

Problem

Phase-locked loops (PLLs) face challenges in achieving both high resolution and large delay ranges for clock signals, as existing analog delay methods provide high resolution but limited range, while digital delays offer large ranges but lack precision.

Innovation Solution

The use of time-to-digital converters (TDCs) in conjunction with memory to sample clock signals and store digital representations of their edges, allowing for high-resolution and large-range delays by queuing and dequeuing these digital values after a predetermined delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If analog delays are used to delay input signals, then high resolution is achieved, but large delay ranges cannot be accommodated

Engineering Contradiction:

Improvedelay resolutionVSAvoiddelay range

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The delay function is segmented into two distinct components: an analog delay chain for high-resolution timing and a digital counter for large-range delay selection. The analog delay provides fine-grained resolution while the digital counter selects from multiple delay intervals, together achieving both high resolution and large delay range that neither component could achieve alone.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If digital delays are used to delay input signals, then large delay ranges are achieved, but high resolution is lost

Engineering Contradiction:

Improvedelay rangeVSAvoiddelay resolution

Core Design Contradiction:

Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The delay function is segmented into two distinct components: an analog delay chain for high-resolution timing and a digital counter for large-range delay selection. The analog delay provides fine-grained resolution while the digital counter selects from multiple delay intervals, together achieving both high resolution and large delay range that neither component could achieve alone.

Inventive Principle:

Principle #1Segmentation

3Reliability

If PLL switches between reference clock signals, then reliability is improved, but signal degradation impact increases

Engineering Contradiction:

Improveclock signal reliabilityVSAvoidsignal degradation impact

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The quality analysis of reference clock signals is performed in advance before switching occurs. The PLL monitors and evaluates the quality of alternative reference clock signals beforehand, so that when a switch is needed, it can transition to a pre-validated high-quality signal rather than switching to a degraded signal, thereby maintaining reliability while minimizing the impact of signal degradation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12019406B2Using time-to-digital converters to delay signals with high accuracy and large range

Publication Date: 2024.06.25 SKYWORKS SOLUTIONS INC

AI summary

A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.