Time-to-Digital Converter Synchronization for Coarse-Fine Code Accuracy
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Solution Overview
Problem
Existing time to digital converters suffer from reduced conversion accuracy due to code errors in the connection between coarse and fine TDC data, leading to inconsistencies in time interval measurements.
Innovation Solution
A time to digital converter design that includes a first circuit for generating lower order bits, a second circuit for higher order bits, and a third circuit for synchronizing these using a signal with multiple bits, utilizing a synchronization circuit with flip-flop and latch circuits to enhance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If coarse TDC and fine TDC are used together for time interval measurement, then measurement range is improved, but conversion accuracy deteriorates due to code errors in connection between coarse and fine TDC data
Solution Approach 1:
A synchronization circuit is introduced as an intermediary component between the fine TDC and coarse TDC. This circuit includes a first latch circuit that holds the fine TDC output signal and a second latch circuit that holds the coarse TDC output signal, with a synchronization signal generation circuit that generates synchronization signals based on these held signals. This intermediary synchronization mechanism ensures proper timing alignment between fine and coarse data, preventing code errors while maintaining extended measurement range.
Solution Approach 2:
The synchronization circuit performs preliminary actions by holding the fine TDC output signal in the first latch circuit and generating synchronization signals before the coarse TDC output signal is processed. This preliminary holding and synchronization of signals ensures that the fine and coarse data are properly aligned in time before being combined, preventing code errors that would otherwise occur due to timing mismatches.
2Measurement precision
If synchronization circuit with latch circuits is added, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The synchronization circuit is segmented into distinct functional units: a first latch circuit for holding the fine TDC output signal, a second latch circuit for holding the coarse TDC output signal, and a synchronization signal generation circuit. This segmentation allows each component to perform its specific function independently, making the overall complex circuit more manageable and easier to implement while achieving the goal of improved conversion accuracy through proper signal synchronization.
Data Source
AI summary
Provided is a time to digital converter that outputs time interval digital data having multiple bits according to a time interval from a first timing to a second timing, the time to digital converter including a first circuit configured to generate lower order bits among the multiple bits, a second circuit configured to generate higher order bits among the multiple bits, and a third circuit configured to synchronize the first circuit and the second circuit by generating a second signal with use of a first signal output from the first circuit and outputting the second signal to the second circuit, in which the first signal is generated by using a signal with multiple bits among the lower order bits.