Time to Digital Converter with Control Signal Gating for Start-Stop Order Errors

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Solution Overview

Problem

A time to digital converter (TDC) fails to correctly measure time when the stop signal is received before the start signal, leading to measurement errors.

Innovation Solution

The TDC is configured with a first measurement block that activates a control signal upon start signal activation and measures time to a common clock signal's edge, and one or multiple second measurement blocks that include lower and upper measurement circuits, enabling them only after the control signal is activated, thus preventing premature stop signal reactions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the TDC measures time continuously without signal validation, then measurement speed is improved, but measurement accuracy deteriorates when stop signal is received before start signal

Engineering Contradiction:
Improvemeasurement speedVSAvoidtime measurement accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The control signal activation in the first measurement block serves as a preliminary action that validates the timing condition before enabling the second measurement block. By checking whether the start signal has been received and activating the control signal accordingly, the system prevents premature measurement attempts that would occur if the stop signal arrived before the start signal, thus maintaining measurement accuracy without sacrificing speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The control signal acts as an intermediary between the start signal and the second measurement block. This intermediary mechanism ensures that the second measurement block is only enabled when the proper timing condition is met (start signal received), thereby preventing measurement errors while maintaining continuous operation capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If the second measurement block is always enabled, then measurement responsiveness is improved, but measurement errors increase when stop signal arrives before start signal

Engineering Contradiction:
Improvemeasurement responsivenessVSAvoidmeasurement reliability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The control signal activation serves as a preliminary enablement condition that is established in advance based on start signal reception. This preliminary action ensures the second measurement block is ready to operate immediately when conditions are met, maintaining responsiveness while preventing erroneous measurements through the gating control mechanism.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The enablement state of the second measurement block is made dynamic rather than static. It transitions from disabled to enabled state based on the reception of the start signal and activation of the control signal. This dynamic control allows the system to adapt its responsiveness to actual measurement conditions, ensuring reliability by preventing operation during invalid states while maintaining quick response when valid.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250113115A1Time to digital converter, distance measuring device, and moving body
Publication Date: 2025.04.03 CANON KK
  • US20250113115A1 patent drawing
  • US20250113115A1 patent drawing
  • US20250113115A1 patent drawing

AI summary

A time to digital conversion circuit includes a first measurement block and one or a plurality of second measurement blocks. The first measurement block activates a control signal in accordance with activation of a start signal and measures time from the activation of the start signal to a first edge of a common clock signal. The second measurement block includes a lower measurement circuit and an upper measurement circuit, which are enabled by the activation of the control signal. The lower measurement circuit measures time from activation of a stop signal to a second edge of the common clock signal, and the upper measurement circuit measures time from the first edge to the second edge.