Time-to-Digital Converter Layout for Smaller Delay Measurement Circuits
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Solution Overview
Problem
Conventional time to digital converting (TDC) circuits require a complete delay circuit, resulting in a larger circuit area and inefficient use of resources.
Innovation Solution
A TDC circuit comprising a first and second delay circuit, a first and second counter, and a comparator, where the first delay stage has a larger delay amount than the second, allowing the first counter to start counting earlier and the comparator to output a result when the second counter value falls within a predetermined range of the first counter value, reducing the required circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a complete delay circuit is used in conventional TDC circuits, then accurate delay measurement is achieved, but circuit area becomes larger
Solution Approach 1:
The delay circuit is segmented into two parts: a first delay circuit with larger delay amount and a second delay circuit with smaller delay amount. This segmentation allows the system to use fewer total delay stages while maintaining measurement accuracy, thereby reducing circuit area.
Solution Approach 2:
Different delay stages are assigned different delay amounts based on their position and function. The first delay circuit uses larger delay stages for coarse measurement, while the second delay circuit uses smaller delay stages for fine measurement, optimizing the overall circuit area while maintaining precision.
2Measurement precision
If more delay stages are used to improve measurement resolution, then measurement precision improves, but device complexity increases
Solution Approach 1:
The measurement process is segmented into two phases: coarse measurement using the first delay circuit with larger delay stages, and fine measurement using the second delay circuit with smaller delay stages. This reduces the total number of delay stages needed while maintaining high resolution.
Solution Approach 2:
The system dynamically switches between different delay circuits and counting modes depending on the measurement requirements, allowing flexible adjustment of measurement resolution without proportionally increasing circuit complexity.
Data Source
AI summary
A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.