TDC Duty Cycle Correction for SerDes Signal Distortion
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Solution Overview
Problem
Conventional methods for signal distortion correction in communication systems, such as asynchronous statistical sampling and analog filtering, introduce complexity and area usage issues, and are sensitive to noise, reducing link reliability and margin in serializer/deserializer (SerDes) systems.
Innovation Solution
A self-triggering time-to-digital converter (TDC) system that determines the duty cycle of signals by delaying and inverting them to calculate the duration of signal portions, allowing for precise adjustment of the duty cycle without additional complex circuitry or area usage, thereby correcting signal distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If asynchronous statistical sampling is used to correct signal distortion, then measurement precision is improved, but device complexity increases due to additional clock signals and routing
Solution Approach 1:
The patent extracts the essential function of signal distortion correction by removing the complex asynchronous sampling clock generation and routing infrastructure. Instead, it uses a simplified duty cycle detection mechanism that directly measures and corrects distortion without requiring additional clock signals or complex sampling infrastructure.
Solution Approach 2:
Rather than using complex asynchronous sampling to detect distortion, the patent inverts the approach by using simple duty cycle detection and correction. The system inverts the problem-solving strategy: instead of sophisticated measurement, it employs straightforward duty cycle analysis that achieves correction with minimal added complexity.
2Measurement precision
If analog filtering of clock signals is used to determine average signal value, then measurement precision is improved, but area usage increases due to additional circuitry
Solution Approach 1:
The patent replaces expensive, area-consuming analog filtering circuitry with a simpler, more economical duty cycle detection approach. The solution uses minimal circuit elements that consume far less silicon area while achieving the same measurement precision for signal distortion correction.
Solution Approach 2:
The patent substitutes complex analog filtering hardware with a digital-duty-cycle-based measurement system. This replacement eliminates the need for physical analog filter components, reducing the circuit area significantly while maintaining measurement accuracy through digital processing of the duty cycle information.
3Reliability
If conventional signal distortion correction methods are used, then reliability is improved, but sensitivity to system noise increases
Solution Approach 1:
The patent implements a self-correcting duty cycle detection mechanism that inherently compensates for noise effects. The system uses the signal itself to detect and correct distortion, creating a feedback loop that automatically adjusts for noise-induced variations without requiring additional noise filtering or complex error correction infrastructure.
Data Source
AI summary
A system includes a first device coupled with a link which transmits a signal having a repeating pattern, and a second device coupled with the link. The second device is to receive the signal, generate one or more delayed signals from the signal, determine a first duration of a first portion of the repeating pattern and a second duration of a second portion of the repeating pattern using the one or more delayed signals, and adjust a current duty cycle of the signal based on the first duration and the second duration.