TDC-Driven Digital Loop Filter Clocking for Low-Jitter DPLLs

Solution Overview

Problem

In digital phase-locked loops (DPLLs), the asynchronous digital bits received by the digital loop filter from the time-to-digital converter are out of sync with the input reference clock, requiring an additional synchronization stage that increases delay, jitter, cost, and chip area.

Innovation Solution

The integration of clock generation circuitry within the time-to-digital converter generates a filter clock synchronized with the phase error values, eliminating the need for an external synchronization circuit by triggering clock pulses from the last-received pulses of both the input and feedback clocks, thus synchronizing the phase error values with the filter clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate synchronization circuit is employed between TDC and DLF to synchronize the reference clock to the digital bits, then the digital bits are synchronized with the reference clock, but this adds another clock cycle delay, increases jitter, and adds cost and area

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidclock cycle delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the clock generation function into the TDC by having the TDC generate both the phase error values and the filter clock simultaneously. This eliminates the separate synchronization circuit and its associated delay, as the digital bits are inherently synchronized with the filter clock from the moment of generation without requiring an additional synchronization stage.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The TDC is given a dual function: it not only measures the phase difference to generate phase error values but also generates the filter clock that drives the DLF. This multi-functionality eliminates the need for a dedicated synchronization circuit, reducing both area and delay while maintaining synchronization accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a separate synchronization circuit is employed between TDC and DLF, then the digital bits are synchronized with the reference clock, but this increases chip area and cost

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the clock generation function into the TDC by having the TDC generate both the phase error values and the filter clock simultaneously. This eliminates the separate synchronization circuit and its associated delay, as the digital bits are inherently synchronized with the filter clock from the moment of generation without requiring an additional synchronization stage.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The TDC is given a dual function: it not only measures the phase difference to generate phase error values but also generates the filter clock that drives the DLF. This multi-functionality eliminates the need for a dedicated synchronization circuit, reducing both area and delay while maintaining synchronization accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If a separate synchronization circuit is employed between TDC and DLF, then the digital bits are synchronized with the reference clock, but this adds another clock cycle and increases jitter

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidjitter

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent merges the clock generation function into the TDC by having the TDC generate both the phase error values and the filter clock simultaneously. This eliminates the separate synchronization circuit and its associated delay, as the digital bits are inherently synchronized with the filter clock from the moment of generation without requiring an additional synchronization stage.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The TDC is given a dual function: it not only measures the phase difference to generate phase error values but also generates the filter clock that drives the DLF. This multi-functionality eliminates the need for a dedicated synchronization circuit, reducing both area and delay while maintaining synchronization accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11677404B1Independently clocking digital loop filter by time-to-digital converter in digital phase-locked loop

Publication Date: 2023.06.13 INFINEON TECHNOLOGIES AMERICAS CORP

AI summary

A time-to-digital converter (TDC) circuit includes phase error calculation circuitry to: determine phase error values based on a time difference between a input reference clock and a feedback clock of a digital phase-locked loop (DPLL) circuit, the input reference clock and the feedback clock being unsynchronized; and provide the phase error values to a digital loop filter (DLF) of the DPLL circuit. The TDC circuit further includes clock generation circuitry to: generate a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock; and provide the filter clock to the DLF concurrently with providing the phase error values to the DLF that are synchronized to the filter clock.