Digital TDC Frequency Measurement Circuit

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Solution Overview

Problem

Existing phase and frequency measuring devices face challenges in achieving high precision due to errors from analog circuitry, such as noise and temperature changes, making it difficult to downsize and reduce costs while measuring phase differences and frequencies accurately.

Innovation Solution

A digital circuit-based phase measuring device and frequency measuring device using Time to Digital Converter (TDC) technology with buffer delay amount measuring circuits and phase difference calculating mechanisms, synchronized with precise reference signals like GPS, to measure phase and frequency differences with high precision without analog circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If analog circuitry (time-voltage conversion circuit and ADC circuit) is used to measure phase differences, then measurement precision can be achieved, but noise, offset, and temperature changes cause errors, and downsizing and cost-reduction become difficult

Engineering Contradiction:
Improvephase difference measurement precisionVSAvoidmeasurement reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent replaces the mechanical/analog time-voltage conversion circuit and ADC circuit with a digital circuit implementation. Specifically, it uses a Time-to-Digital Converter (TDC) that converts time intervals directly into digital values through counter circuits, eliminating the need for analog components. This substitution resolves the contradiction by maintaining measurement precision through digital counting while eliminating noise, offset, and temperature-related errors inherent in analog circuitry.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental measurement parameter from voltage (analog) to time intervals (digital). Instead of converting time to voltage and then to digital values, the system directly measures time intervals using clock signals and counters, converting them into digital representations. This parameter change enables high-precision measurement without the reliability issues of analog circuitry.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If analog circuitry (time-voltage conversion circuit and ADC circuit) is used to measure phase differences, then measurement precision can be achieved, but the number of circuit components increases, making downsizing and cost-reduction difficult

Engineering Contradiction:
Improvephase difference measurement precisionVSAvoidcircuit configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces multiple analog circuit components (time-voltage conversion circuit, ADC circuit, and associated support circuits) with a integrated digital TDC circuit. The digital implementation uses clock signals, counters, and logic circuits that can be implemented on a single chip, significantly reducing the number of discrete components and enabling downsizing while maintaining measurement precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent merges the functions of time measurement, voltage conversion, and digital conversion into a single digital TDC circuit block. By combining these previously separate analog and digital functions into one integrated digital circuit, the overall device complexity is reduced, making downsizing and cost-reduction achievable while preserving measurement precision.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If clock signal wavelengths are shortened to improve measurement precision, then measurement precision increases, but there is a realistic limit to how short the wavelengths of generable clock signals can be

Engineering Contradiction:
Improvemeasurement precisionVSAvoidclock signal frequency
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The patent measures time intervals in a different dimensional approach by using high-frequency clock signals for fine resolution measurement of fractional cycles. Instead of relying solely on lowering clock frequency (lengthening wavelength), the system uses digital counting of clock cycles and fractional cycle measurement through TDC technology, enabling high precision without being constrained by the physical limits of clock signal generation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the time measurement into two parts: integer cycles measured by counting complete clock signal periods, and fractional cycles measured by the TDC circuit with picosecond resolution. This segmentation allows the system to achieve high measurement precision without requiring extremely short clock wavelengths, as the fractional part measurement provides the additional precision needed.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3196661B1Frequency measuring device
Publication Date: 2021.04.21 FURUNO ELECTRIC CO LTD
  • EP3196661B1 patent drawingFigure 1
  • EP3196661B1 patent drawingFigure 2(A)~2(B)
  • EP3196661B1 patent drawingFigure 3

AI summary

A frequency measuring device is disclosed, comprising: a buffer delay amount measuring circuit 610 including a plurality of buffers for being inputted with clock signals that are synchronized with a reference signal calculated by positioning calculation, at different timings shifted by a fixed delay time, respectively, and being simultaneously inputted with a sampling reference signal of a lower frequency than the clock signals, and respectively generating state data according to levels of the clock signals at a transition timing of the sampling reference signal, wherein the buffer delay amount measuring circuit outputs delay measurement data comprised of a group of the state data from the plurality of buffers; a frequency measuring circuit 620 including a plurality of buffers for being inputted with third measuring signals at different timings shifted by a fixed delay time, respectively, being simultaneously inputted with a sampling reference signal of a lower frequency than the third measuring signals, and respectively generating state data according to levels of the third measuring signals at a transition timing of the sampling reference signal, wherein the frequency measuring circuit outputs the frequency measurement data comprised of a group of the state data from the plurality of buffers; and a frequency calculator 62 for calculating the delay amount between the buffers based on the delay measurement data, and calculating a frequency or a cycle of the third measuring signals based on the frequency measurement data and the delay amount.