Time-to-Digital Frequency Synthesizer for Accurate Phase Detection
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Solution Overview
Problem
Existing frequency synthesizers require a large number of frequency delta-sigma modulation units in parallel to accurately measure the frequency ratio between clock signals, leading to a significant increase in circuit scale.
Innovation Solution
A frequency synthesizer that includes a time-to-digital converter, a comparison unit, a frequency adjustment unit, and an oscillation unit, where the time-to-digital converter outputs a time-to-digital value corresponding to the phase difference between the operating clock signal and the trigger signal, allowing for phase detection and frequency adjustment without the need for multiple delta-sigma modulation units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a large number of frequency delta-sigma modulation units are provided in parallel to accurately measure the frequency ratio, then the frequency measurement accuracy is improved, but the circuit scale significantly increases
Solution Approach 1:
The patent replaces the frequency delta-sigma modulation units with a time-to-digital converter that measures the time difference between clock signals and converts it to a digital value. This substitution of measurement mechanism eliminates the need for multiple parallel modulation units, thereby maintaining frequency measurement accuracy while significantly reducing circuit scale
Solution Approach 2:
The patent introduces a time-to-digital converter as an intermediary device that bridges the measurement of time difference and frequency ratio. By measuring the time difference between clock signals and converting it to a digital value, the TDC acts as a mediator that achieves accurate frequency measurement without requiring multiple parallel units, thus reducing circuit complexity
Data Source
AI summary
A frequency synthesizer includes: a time-to-digital converter configured to output a time-to-digital value corresponding to a time event of a trigger signal with respect to an operating clock signal; a comparison unit configured to compare a value based on the time-to-digital value with a target value; an oscillation unit configured to generate the synthesizer signal; and a frequency adjustment unit configured to adjust a frequency of the synthesizer signal based on a comparison result of the comparison unit. The time-to-digital converter includes: a state transition unit configured to start a state transition in which an internal state transitions based on the time event of the trigger signal and output state information indicating the internal state; a transition state acquisition unit configured to acquire and hold the state information in synchronization with the operating clock signal; and a calculation unit configured to calculate the time-to-digital value according to the number of transition times of the internal state based on the state information acquired by the transition state acquisition unit.