Time-to-Digital Converter Gain Calibration for Low-Spur Clocks

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Solution Overview

Problem

Existing clock generators using time-to-digital converters face issues with gain error, which increase noise and spurs in the output, due to mismatched gains between coarse and fine converters, affecting the accuracy of clock signals.

Innovation Solution

A calibration technique is implemented using a virtual phase-locked loop and a least mean squares adaptive loop to generate a calibration signal that adjusts the gain of the fine time-to-digital converter to match the coarse converter's gain, reducing phase noise and spurs by correlating digital error signals and averaging them over multiple cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a time-to-digital converter is used to generate digital signals from clock signals, then clock signal generation is enabled, but gain error increases noise and spurs in the output

Engineering Contradiction:

Improveclock signal generation capabilityVSAvoidnoise and spurs in output

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a feedback mechanism where the digital output from the time-to-digital converter is fed back through a virtual phase-locked loop to generate a calibration signal. This calibration signal is used to adjust the TDC's gain, creating a closed-loop system that automatically compensates for gain errors and reduces noise and spurs in the output clock signal.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the gain parameter of the time-to-digital converter dynamically using a calibration signal generated by the virtual phase-locked loop. By adjusting the TDC gain based on detected phase errors and applying least mean squares adaptation, the system optimizes the converter's performance to minimize noise and spurs while maintaining clock generation capability.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If gain of fine time-to-digital converter is increased to improve resolution, then measurement precision improves, but gain mismatch with coarse converter increases error

Engineering Contradiction:

Improvetime measurement resolutionVSAvoidgain matching between converters

Core Design Contradiction:

Measurement precisionVSManufacturing precision

Solution Approach 1:

The patent introduces a virtual phase-locked loop as an intermediary system that mediates between the coarse and fine time-to-digital converters. This intermediary generates a calibration signal that adjusts the fine converter's gain to match the coarse converter, enabling high resolution measurement while maintaining gain compatibility between the two converters through adaptive calibration.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11283459B1Calibration of a time-to-digital converter using a virtual phase-locked loop

Publication Date: 2022.03.22 SKYWORKS SOLUTIONS INC

AI summary

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.