TDC Input Switching for Wider Time Delay Range in PLLs
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Solution Overview
Problem
Time to digital converters (TDCs) in digital phase-locked loops (PLLs) face limitations in dynamic range, which affects their ability to accurately measure time delays between signals, leading to increased errors and jitter, particularly in fractional PLLs where deterministic disturbances cause fractional errors.
Innovation Solution
The method involves a TDC with an input network that switches and outputs signals based on a sign value, using a plurality of delay elements and memory elements to generate a digital code value representing time delays, and an offset calibration signal to reduce errors, effectively doubling the dynamic range while maintaining power and area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC measures time delay between signals, then it generates a digital code value representing the delay, but the dynamic range is limited affecting measurement accuracy
Solution Approach 1:
The patent implements dynamic signal switching in the TDC input network based on the sign value of the time delay. The switches dynamically reconfigure the signal paths depending on whether the delay is positive or negative, allowing the TDC to adapt its measurement range. This dynamic reconfiguration enables the system to handle both small and large time delays accurately, effectively doubling the dynamic range while maintaining measurement precision.
2Measurement precision
If the TDC dynamic range is increased to measure both positive and negative delays, then measurement accuracy improves, but device complexity increases
Solution Approach 1:
The patent makes the existing TDC structure multi-functional by adding a control mechanism that routes signals based on the sign value. The same TDC core circuit processes both positive and negative time delays by dynamically switching its input configuration. This universal approach allows one TDC structure to perform multiple measurement functions without requiring separate dedicated circuits for positive and negative delays, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent introduces switches as intermediary elements between the signal inputs and the TDC core. These switches act as mediators that dynamically reconfigure the signal paths based on the sign value, enabling the TDC to measure both positive and negative delays without directly modifying the core TDC structure. This intermediary approach isolates the complexity to the switching control logic while preserving the simplicity of the main TDC circuit.
3Adaptability or versatility
If signal switching is implemented based on sign value, then dynamic range is doubled, but power consumption increases
Solution Approach 1:
The signal switching operation occurs periodically at the rising edge of the reference signal, synchronized with the PLL operation. This periodic switching is controlled by the sign value determined from the time delay measurement. By timing the switching events to coincide with natural signal transitions in the PLL, the patent minimizes additional power consumption that would result from continuous or unsynchronized switching operations.
4Measurement precision
If fractional error correction is applied in PLL, then phase lock accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements feedback by using the sign value (determined from the time delay measurement) to control the switching of signal paths in subsequent measurement cycles. This feedback mechanism allows the PLL to correct fractional errors by adjusting the signal routing based on previous delay measurements, improving phase lock accuracy without requiring complex external correction circuits.
Data Source
AI summary
An apparatus increases the dynamic range of a time to digital converter. The apparatus includes: an input network configured to receive a first signal, a second signal, and a control signal having a sign value; and a time-to-digital converter (TDC) configured to generate a digital code value that represents a time delay value between the first signal and the second signal. The input network is configured to switch where the first signal and second signal are output in response to the sign value that is determined by the time delay value between the first signal and the second signal.