TDC Linear Calibration in Digital PLLs for Phase Alignment
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Solution Overview
Problem
Time-to-digital converters in all-digital phase-locked loops suffer from low resolution, complex circuit structures, and high power consumption due to semiconductor process variations, leading to inaccuracies.
Innovation Solution
A linear calibration system comprising a digitally controlled reference delay circuit, a time-to-digital conversion circuit, and a state machine that adjusts calibration control signals to align the phase of delay signals with a reference clock signal, improving the linearity and accuracy of time-to-digital converters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional analog components are replaced with digital components in phase-locked loops, then integration level and system compatibility are improved, but time-to-digital converter resolution and accuracy deteriorate due to semiconductor process variations
Solution Approach 1:
The patent applies preliminary action by performing calibration before normal operation. A calibration mode is implemented where the TDC is pre-calibrated to compensate for process variations, ensuring high resolution and accuracy are achieved during subsequent working mode operation without requiring complex circuit structures
Solution Approach 2:
The patent changes operational parameters by switching between calibration mode and working mode. During calibration mode, specific control signals are adjusted to optimize TDC performance, and these parameter settings are then used during normal operation to maintain high resolution while using simpler digital circuit structures
2Measurement precision
If complex circuit structures are used to improve time-to-digital converter accuracy, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
Instead of using complex circuit structures continuously, the patent performs preliminary calibration to establish accurate operating parameters. This preliminary action stores compensation data that simplifies the circuit structure requirements during normal operation, reducing both complexity and power consumption while maintaining accuracy
Solution Approach 2:
The patent extracts the calibration function as a separate operational mode distinct from normal TDC operation. By separating calibration activities from continuous measurement functions, the circuit can use simpler structures during measurement while achieving high accuracy through the extracted calibration process
Data Source
AI summary
The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.