TDC Loopback Linearity Testing in Digital PLL Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The linearity of time-to-digital converter circuits in digital phase-locked loop circuits is difficult to accurately measure, leading to increased jitter in output clock signals due to non-linearities, which affects the performance of digital PLLs.
Innovation Solution
A test circuit is implemented that includes a control circuit generating stimulus code values to test the linearity of time-to-digital converter circuits by comparing digital outputs with captured codes, using a digital-to-time converter circuit to provide delayed signals, allowing for calibration to compensate for non-linearities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time-to-digital converter circuits are used in digital phase-locked loop circuits, then the phase comparison function is achieved, but non-linearities in the converter cause increased jitter in output clock signals
Solution Approach 1:
The patent applies preliminary action by performing linearity testing and calibration of the time-to-digital converter before the digital phase-locked loop operates in its normal mode. The test circuit characterizes the TDC's non-linearities in advance, and calibration data is stored for later compensation during actual operation, thereby reducing jitter in output clock signals
Solution Approach 2:
The patent implements feedback by using the measured linearity characteristics of the TDC to generate calibration data that compensates for non-linearities. The control circuit compares stimulus codes with captured codes, determines linearity errors, and uses this feedback information to adjust or compensate the TDC operation, thereby improving measurement precision and reducing output jitter
2Extent of automation
If traditional phase comparison circuits are replaced with time-to-digital converter circuits, then digital processing capability is improved, but difficulty in measuring and testing linearity increases
Solution Approach 1:
The patent introduces an intermediary test circuit that includes a digital-to-time converter and a control circuit. This intermediary system facilitates the measurement of TDC linearity by generating known stimulus codes, converting them to time delays, capturing the TDC output, and comparing the results. This intermediary testing mechanism simplifies the detection and measurement process while maintaining digital processing advantages
Data Source
AI summary
A phase-locked loop circuit included in a computer system includes time-to-digital converter and digital-to-time converter circuits. During a mode to test the time-to-digital converter circuit, the digital-to-time converter circuit is coupled to the time-to-digital converter circuit in a loop-back fashion. A control circuit supplies stimulus codes to the digital-time-converter circuit, which generates multiple delayed versions of a reference clock signal using the stimulus codes. The time-to-digital converter circuit, in turn, generates capture codes based on the delay between the reference clock signal and the delayed versions of the reference clock signal. The control circuit compares the capture codes to the stimulus codes to determine a linearity of a response of the time-to-digital converter circuit.