Configurable TDC Multiplier for Low-Complexity Fractional Error Correction
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Solution Overview
Problem
All-digital phase locked loops (ADPLLs) face complexity and power consumption issues due to the need for multiple multipliers with large bit sizes in fractional error detection units, leading to increased size and power consumption.
Innovation Solution
Incorporating a time-to-digital converter (TDC) configured to transmit and receive data to reduce the bit size of multipliers, and using a configurable multiplier with selectable bit sizes to simplify the Newton-Raphson method for determining the reciprocal of the variable clock period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple multipliers with large bit sizes are used in fractional error detection units, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies a single configurable multiplier that can be dynamically adjusted to perform multiple multiplication operations with different bit sizes. This multiplier is reused across different stages of the Newton-Raphson method for reciprocal calculation, eliminating the need for multiple dedicated multipliers while maintaining the required precision for phase difference measurement.
2Measurement precision
If multiple multipliers with large bit sizes are used in fractional error detection units, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The configurable multiplier serves multiple functions by being dynamically reconfigured for different multiplication operations. Instead of having multiple static multipliers operating simultaneously and consuming power continuously, a single multiplier is reused sequentially with adjustable bit width, significantly reducing overall power consumption while maintaining measurement precision.
3Measurement precision
If multiple multipliers with large bit sizes are used in fractional error detection units, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent implements a single configurable multiplier that can be dynamically reconfigured to different bit sizes. This approach reduces the silicon area required compared to having multiple fixed-size multipliers, as the configurable multiplier shares the same physical resources across different operational modes, thereby minimizing the area occupied in the fractional error detection unit.
4Device complexity
If a configurable multiplier with selectable bit sizes is used, then device complexity is reduced, but adaptability decreases
Solution Approach 1:
The patent employs a dynamic configuration approach where the multiplier's bit size is adjusted in real-time based on the specific computational requirements of each Newton-Raphson iteration. This dynamic adaptability allows the system to optimize between precision and resource usage for different operational phases, maintaining versatility while simplifying the overall device architecture compared to having multiple fixed multipliers.
Data Source
AI summary
A fractional error correction circuit includes a time-to-digital converter (TDC) configured to detect a phase difference between a reference clock signal and a variable clock signal, and a configurable multiplier coupled with the TDC. The configurable multiplier has a selectable bit size, the selectable bit size being based on a minimum number of bits needed to obtain a reciprocal of a period of the variable clock signal. The TDC is configured to output a fractional error correction value based on the detected phase difference and the reciprocal of the period.