TDC-Based Oscillator Frequency Calibration Under Tight Idle Time

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Solution Overview

Problem

Existing frequency calibration (FCAL) techniques in Bluetooth Low Energy applications require a lengthy calibration time, which can exceed the limited idle mode duration, necessitating a faster clock source and increasing digital power consumption.

Innovation Solution

A novel FCAL circuit and method utilizing a controllable oscillator, divider, time-to-digital converter (TDC), and calibration logic to rapidly calibrate the oscillation frequency by comparing fractional period codes, thereby reducing calibration time without increasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the FCAL time period is extended to improve calibration accuracy, then measurement precision is improved, but the idle mode time budget is exceeded and digital power consumption increases

Engineering Contradiction:
ImproveFCAL accuracyVSAvoididle mode time budget
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent replaces the conventional counter-based time measurement mechanism with a time-to-digital converter (TDC) that uses phase comparison. This substitution enables fractional period measurement capability, achieving high-precision FCAL in a shorter time period by converting time interval measurement into phase difference detection, which can be resolved with higher precision without extending the measurement duration.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If a higher clock rate is used to complete FCAL within limited idle mode time, then productivity is improved, but digital power consumption increases

Engineering Contradiction:
ImproveFCAL completion speedVSAvoiddigital power consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent introduces a time-to-digital converter (TDC) as an intermediary component between the oscillator and the calibration logic. The TDC converts time interval measurements into digital values through phase comparison, enabling accurate FCAL measurements without requiring high-speed digital counters. This intermediary mechanism allows the system to complete FCAL at the regular clock rate without increasing power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If conventional FCAL techniques are used to meet strict channel switching time requirements, then productivity is improved, but measurement precision deteriorates

Engineering Contradiction:
Improvechannel switching speedVSAvoidFCAL accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent transitions from measuring time intervals using integer cycle counting to measuring phase differences within a cycle. By adding the dimensional aspect of fractional phase measurement, the system achieves high precision FCAL results within the strict time constraints of channel switching operations. The TDC measures the phase position within a clock cycle, providing sub-cycle resolution that integer counters cannot achieve.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12308842B2Frequency calibration circuit and method for calibrating oscillation frequency of controllable oscillator
Publication Date: 2025.05.20 MEDIATEK INC
  • US12308842B2 patent drawing
  • US12308842B2 patent drawing
  • US12308842B2 patent drawing

AI summary

A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.