Time-to-Digital Converter Oversampling for Lower DPLL Phase Noise

The patent segments the TDC operation into two distinct domains: a high-frequency domain for performing phase comparisons at a higher rate to reduce noise, and a lower-frequency domain for processing the results. This segmentation allows the system to achieve better phase noise performance through oversampling while keeping the power consumption of the processing circuitry at manageable levels by not running all circuits at the high frequency continuously.

The patent implements dynamic operation by allowing the TDC to operate at different frequencies in different domains. The comparison circuit operates at a higher frequency to capture more phase information, while the processing circuit dynamically processes this information at appropriate rates. This dynamic approach enables the system to adapt its operating frequency to the specific requirements of noise reduction versus power consumption.

The patent extracts the noise reduction function from the TDC architecture itself and relocates it to the signal processing domain. Instead of modifying the TDC hardware to reduce noise, the system performs phase comparisons at a higher rate and then applies digital signal processing techniques to filter and process the results. This extraction approach reduces phase noise without requiring complex architectural changes to the TDC itself.

The patent substitutes mechanical/architectural modifications of the TDC with digital signal processing methods. Rather than redesigning the TDC circuitry to reduce noise, the system uses digital filtering and processing of the high-rate comparison results to achieve noise reduction. This substitution of digital processing for hardware modification simplifies the overall architecture while achieving the desired performance.