Time-to-Digital Converter Calibration for Accurate Phase Measurement
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Solution Overview
Problem
Existing fractional phase detectors face inaccuracies due to unknown delays and integer multiple period issues, affecting phase measurement precision and accuracy, especially when the reference signal period is an integer multiple of the clock signal, and different reaction times to logical transitions.
Innovation Solution
A circuit comprising a time to digital converter and an oscillator circuit with a calibration mode that selects multiple transitions of the oscillator signal to control timing, allowing for the elimination of unknown delays and relative calibration of phase components, reducing jitter and enabling fast calibration through programmable translation and polarity selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a TDC measures time delay between clock signal and reference signal transitions, then phase measurement precision is improved, but unknown delays in the delay circuit and different reaction times to logical transitions cause measurement inaccuracy
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual phase measurements. The calibration mode measures time delays for both up-transitions and down-transitions of the oscillator signal, storing these calibration values to compensate for unknown delays and reaction time differences during normal operation. This pre-characterization of the delay circuit eliminates the accuracy problems caused by unknown delays.
Solution Approach 2:
The patent implements feedback by using the calibration measurements to adjust and correct the phase measurement process. The control circuit stores calibration values representing the time delays for different transition types, and uses these values to compensate for delays in subsequent phase measurements. This feedback mechanism ensures that the phase detector accurately accounts for circuit-specific delays.
2Device complexity
If the period of the reference signal is an integer multiple of the clock signal period, then the phase detector can operate with simpler timing, but the TDC may not produce useful results due to synchronization issues
Solution Approach 1:
The patent uses the oscillator signal as an intermediary to bridge the reference signal and the delay circuit. By measuring the time delay between transitions of the oscillator signal (which is derived from the reference signal) and the corresponding transitions at the output of the delay circuit, the system can accurately measure phase differences even when the reference signal period is an integer multiple of the clock period. The oscillator signal acts as a mediator that enables meaningful TDC operation in these conditions.
3Measurement precision
If multiple transitions of the oscillator signal are used to control timing in calibration mode, then unknown delays are eliminated and calibration accuracy is improved, but the calibration process requires more measurements and time
Solution Approach 1:
The patent applies periodic action by using the oscillating oscillator signal to periodically trigger calibration measurements. The calibration mode measures time delays at multiple periodic transitions (both up-transitions and down-transitions) of the oscillator signal. This periodic sampling approach efficiently captures the delay characteristics of the circuit while maintaining accuracy, and the measurements can be performed in a systematic sequence that minimizes total calibration time.
Data Source
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AI summary
Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit (20) of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit (22) with a delay circuit input and a plurality of taps outputs respective, differently delayed versions of a signal from a delay circuit input. A sampling register (24) has data inputs coupled to the taps, and samples data from the data inputs in response to an active transition at a clock input. When in the normal operating mode, the feed circuit (2) feeds an oscillator signal of an oscillator circuit (10) to the delay circuit input and a reference signal to the clock input of the sampling register (24). When in the calibration mode, the feed circuit (20) supplies signals with transitions having timing controlled by the oscillator signal to both the delay circuit input and the clock input. The feed circuit (20) provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit (28) switches the feed circuit between the normal operating mode and the calibration mode, and controls the feed circuit (20) successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register (24) for each selection and determine calibration data for the oscillator signal from said data.