Time-to-Digital Conversion with Phase-Controlled Delay Alignment
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Solution Overview
Problem
The existing time-to-digital conversion devices suffer from conversion accuracy deterioration due to code errors at the boundary between upper and lower TDC data.
Innovation Solution
A time-to-digital conversion device is configured with a first circuit for upper counter generation, a second circuit for lower counter operation, and a control circuit to manage the phase of a delay element, utilizing a common PLL circuit to synchronize and correct the phase of multiphase VCOs or voltage-controlled delay lines, reducing code errors and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a time-to-digital conversion device uses upper and lower TDC circuits to measure time intervals, then the measurement range is extended, but code errors occur at the boundary between upper and lower TDC data causing deterioration in conversion accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector detects phase differences between the clock signal and delay element output, and the control circuit adjusts the delay element's phase based on this detection to correct boundary code errors between upper and lower TDC data
Solution Approach 2:
The patent introduces a delay element with controllable phase as an intermediary component between the upper and lower TDC circuits. This delay element, controlled by the control circuit, compensates for phase mismatches and eliminates code errors at the data boundary
2Device complexity
If the phase of the delay element is not controlled, then the circuit operation is simple, but code errors occur at the boundary between upper and lower TDC data
Solution Approach 1:
The patent dynamically adjusts the phase parameter of the delay element based on the detected phase difference. By changing the phase parameter of the delay element under control of the control circuit, the system eliminates boundary code errors while maintaining relatively simple circuit architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high-precision time-to-digital conversion by minimizing code errors at the boundary between upper and lower TDC data, ensuring accurate time digital data generation while reducing power consumption.
Implementation Method 1
a delay element configured to start operation according to the second timing
Implementation Method 2
a control circuit that controls a phase of an output signal of the delay element based on the clock signal
Data Source
AI summary
A time-to-digital conversion device according to an embodiment of the present disclosure is a time-to-digital conversion device configured to output time digital data according to a time from a first timing to a second timing, including a first circuit that includes an upper counter configured to start counting a clock signal according to the first timing, and generates upper bits of the time digital data; a second circuit that includes a delay element configured to start operation according to the second timing and a lower counter configured to count an oscillation cycle of the delay element, and generates lower bits of the time digital data; and a control circuit that controls a phase of an output signal of the delay element based on the clock signal.