Time-to-Digital Converter for Wide-Range Phase and Frequency Detection
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) in all-digital phase-locked loops (ADPLLs) have a limited pull-in range and can only operate effectively with small frequency differences, failing to accurately detect both phase and frequency errors, which restricts their application in advanced process technologies.
Innovation Solution
A TDC design that includes a phase-frequency detector, a converter with series-coupled delay elements, comparators, and a frequency detector, capable of outputting phase and frequency errors as digital codes, allowing for wider pull-in range and accurate detection of both phase and frequency differences between signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-line based TDC or stochastic TDC is used, then the circuit can operate in advanced process technology, but the pull-in range is limited and frequency difference detection is not accurate
Solution Approach 1:
The TDC is segmented into multiple functional modules: a phase detector for phase difference detection, a frequency detector for frequency difference detection, and a digital filter for signal processing. This segmentation allows each module to specialize in specific detection tasks, enabling accurate detection of both phase and frequency differences while maintaining compatibility with advanced process technology
Solution Approach 2:
The TDC is designed with multi-functionality to detect both phase difference and frequency difference between input signals. The phase detector uses delay elements to detect phase differences, while the frequency detector counts cycles to detect frequency differences. This universal detection capability resolves the limitation of existing TDCs that could only function as phase detectors with limited pull-in range
2Reliability
If the loop bandwidth is decreased to reduce jitter, then the pull-in range is reduced
Solution Approach 1:
The TDC implements feedback mechanisms where the phase detector and frequency detector continuously monitor the input signals and provide correction signals to adjust the output frequency. This feedback allows the system to maintain a wide pull-in range while keeping jitter low, as the feedback loop can correct large frequency deviations without requiring a high loop bandwidth
Solution Approach 2:
The TDC dynamically adjusts detection parameters based on the input signal conditions. The frequency detector can switch between different counting modes and the phase detector can adjust its delay element settings to optimize performance for different frequency differences, enabling wide pull-in range while maintaining low jitter through parameter optimization
3Adaptability or versatility
If a bang-bang PFD is used instead of a TDC, then the pull-in range is increased, but the phase-alignment accuracy becomes poor
Solution Approach 1:
The detection system is segmented into a phase detector for accurate phase alignment and a frequency detector for wide pull-in range. The phase detector provides fine phase adjustment with high accuracy, while the frequency detector handles large frequency deviations. This segmentation combines the advantages of both approaches, achieving both wide pull-in range and high phase-alignment accuracy
Solution Approach 2:
The TDC dynamically switches between frequency detection mode and phase detection mode based on the magnitude of frequency difference. When frequency difference is large, the frequency detector is active to expand pull-in range. When frequency difference is small, the phase detector takes over to provide accurate phase alignment. This dynamic operation resolves the contradiction between pull-in range and phase-alignment accuracy
Data Source
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AI summary
A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.