Time-to-Digital Converter Phase Sampling for Low-Power DPLLs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-to-digital converters (TDCs) face challenges in achieving high measurement precision and quantization rate while maintaining low power consumption and minimizing the impact on surrounding components in digital phase-locked loops, as high device counts increase power consumption and cause periodic modulations, and reduced sampling circuits struggle with predicting edge locations, leading to insufficient quantization quality.
Innovation Solution
The implementation of a TDC with overlapping time segments and dual sampling circuits allows for increased sampling elements at a higher rate, maintaining resolution through post-sampling detection and using a lookup table for phase estimation, enabling precise phase difference measurement without excessive power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a flash-TDC with numerous sampling elements is used to achieve high resolution phase quantization, then measurement precision is improved, but power consumption increases and periodic modulations are caused in surrounding components
Solution Approach 1:
The patent divides the time period into multiple overlapping time segments, with each segment handled by a separate sampling circuit. Instead of using all sampling circuits simultaneously, the system activates only the circuit corresponding to the current time segment, thereby achieving high-resolution phase measurement while keeping the active device count low at any given moment, which reduces power consumption and minimizes periodic modulations in surrounding components
Solution Approach 2:
The patent employs periodic switching between different sampling circuits corresponding to different time segments. By cyclically activating sampling circuits in a periodic manner rather than simultaneously, the system maintains high measurement precision while distributing the power consumption over time, preventing the concentrated power draw that would cause periodic modulations in surrounding components
2Use of energy by moving object
If the number of sampling elements is reduced to minimize power consumption, then power consumption is reduced, but quantization quality suffers due to inability to predict edge location with sufficient precision
Solution Approach 1:
The patent performs preliminary actions by pre-dividing the time period into multiple overlapping time segments and pre-assigning sampling circuits to each segment. This preliminary structuring allows the system to know in advance which sampling circuit should be active for any given phase measurement, eliminating the need for complex real-time edge location prediction while maintaining high quantization quality with minimal active sampling elements
Solution Approach 2:
The patent introduces time segments as an intermediary structure between the sampling circuits and the phase measurement process. These time segments act as mediators that organize the measurement process into discrete, manageable intervals, allowing each sampling circuit to operate independently on its assigned segment without requiring complex coordination or prediction mechanisms, thereby maintaining precision with reduced device count
3Productivity
If a high number of circuits operate within a small time segment to achieve high quantization rate, then productivity is improved, but device complexity and impact on surrounding components increase
Solution Approach 1:
The patent segments the time period into multiple overlapping intervals and assigns different sampling circuits to different segments. This segmentation allows the system to achieve high quantization rates by processing multiple time segments in sequence rather than requiring all sampling circuits to operate simultaneously, thereby maintaining high productivity while reducing the number of active circuits at any moment and simplifying the overall device architecture
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A time-to-digital converter may include a delay circuit configured to delay a first signal to generate a plurality of delayed first signals; a circuit configured to generate a first analog oscillating signal and a second analog oscillating signal using an input second signal, wherein the second analog oscillating signal is phase offset with respect to the first analog oscillating signal; a first plurality of sample circuits, each configured to sample the first analog oscillating signal in accordance with an associated delayed first signal of the delayed first signals, and a second plurality of sample circuits, each configured to sample the second analog oscillating signal in accordance with an associated delayed first signal of the delayed first signals. Each of the delayed first signals is provided to a respective sample circuit of the first plurality of sample circuits and to a respective sample circuit of the second plurality of sample circuits.