TDC-Assisted PLL Spur Cancellation for Fractional Spur Mitigation
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Solution Overview
Problem
Fractional phase-locked loops (PLLs) in communication systems suffer from strong fractional spurs, which are difficult to mitigate in the analog domain, especially with the stringent requirements of next-generation communication protocols, leading to inefficient and unreliable spur-level management.
Innovation Solution
A communication system is configured with a time-to-digital converter (TDC) and a digital signal processor (DSP) to determine the phase difference between the reference frequency and the output oscillating signal, estimate the amplitude and phase of the fractional spur, and construct an estimate to cancel it, thereby compensating for the undesired spur in the baseband signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If analog-domain mitigation techniques are used to reduce fractional spurs, then spur level requirements may be met, but circuit isolation requirements increase leading to larger implementation area
Solution Approach 1:
The patent replaces analog-domain mitigation techniques with a digital-domain solution. Instead of using analog circuit isolation methods that require larger physical area, the invention uses digital signal processing to generate compensation signals that cancel fractional spurs. The TDC and DSP components operate in the digital domain to measure phase differences and generate corrective signals, eliminating the need for extensive analog circuit isolation.
Solution Approach 2:
The patent changes the domain of operation from analog to digital. By converting the mitigation approach to digital signal processing, the system can achieve spur reduction without the physical isolation requirements of analog circuits. The digital domain allows for flexible parameter adjustment and compensation signal generation that does not depend on physical circuit layout or isolation distances.
2Object-affected harmful factors
If analog-domain mitigation techniques are used to reduce fractional spurs, then spur level requirements may be met, but current consumption or supply voltage requirements increase
Solution Approach 1:
The patent substitutes high-current analog mitigation circuits with low-power digital signal processing. The TDC and DSP components consume significantly less current than analog mitigation techniques that require large currents or higher supply voltages. The digital domain operations enable efficient spur compensation without the energy-intensive analog circuitry.
3Object-affected harmful factors
If known analog-domain optimization methods are deployed, then some spur mitigation is achieved, but reliability for next generation communication systems remains insufficient
Solution Approach 1:
The patent implements a feedback mechanism where the TDC continuously measures the phase difference between the reference frequency and the output oscillating signal. This real-time measurement feeds into the DSP, which generates compensation signals based on the actual measured phase error. This closed-loop feedback approach ensures reliable and adaptive spur mitigation that can dynamically adjust to changing conditions, meeting stringent requirements for next-generation communication systems.
Solution Approach 2:
The replacement of analog mitigation with digital signal processing provides more reliable and predictable spur reduction. Digital techniques offer better precision, consistency, and adaptability compared to analog methods, ensuring reliable compliance with stringent spur-level requirements in next-generation communication systems.
Data Source
AI summary
Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.