Time-to-Digital Converter with PVT-Invariant Sub-Gate Delay
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Solution Overview
Problem
Existing digital time converters using simple logical gates are susceptible to variations in production process, supply voltage, and temperature (PVT), and their delay resolution is limited by the minimum gate delay of the technology used.
Innovation Solution
The development of a control circuit that includes a first and second delay circuit, each comprising a series of delay elements, to generate control voltages that produce PVT invariant delays with sub-gate resolution, using a reference clock that is invariant to PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If simple logical gates are used to delay electronic signals, then the device complexity is reduced, but the delay resolution is limited by the minimum gate delay and the device becomes susceptible to PVT variations
Solution Approach 1:
The delay line is segmented into multiple identical delay cells, each contributing a fraction of the total delay. By dividing the total delay into N segments, the resolution is improved by a factor of N while using simple logical gates. Each delay cell is replicated N times in parallel, allowing fine-grained control of the overall delay without requiring complex circuitry.
Solution Approach 2:
The patent introduces dynamic control signals to selectively enable or disable specific delay cells based on the desired delay value. This dynamic configuration allows the delay line to achieve variable delay with sub-gate resolution by activating only the necessary number of delay cells, rather than using a single complex delay circuit.
2Reliability
If the delay line is made invariant to PVT variations, then the reliability is improved, but the device complexity increases due to additional control circuits
Solution Approach 1:
The patent changes the operating parameters of the delay cells by applying control voltages that adjust the propagation delay of each cell. By dynamically adjusting the delay parameter of individual cells based on PVT conditions, the system maintains PVT invariance without requiring complex compensation circuits, as the simple logical gates are reconfigured to operate at optimized points.
3Measurement precision
If multiple delay circuits are used to achieve sub-gate resolution, then the delay resolution is improved, but the device complexity and power consumption increase
Solution Approach 1:
Instead of activating all delay cells simultaneously, the patent enables only the necessary subset of delay cells required to achieve the desired delay value. This partial action approach reduces power consumption significantly, as only a fraction of the total delay cells are active at any given time, while still achieving sub-gate resolution through the selective combination of delay segments.
Data Source
AI summary
A control circuit and a method for delaying an electronic signal are provided, along with a time-to-digital converter including the control circuit. The example control circuit includes a first delay circuit having a first plurality of delay elements electrically connected in series and configured to generate a first control voltage associated with a first delay time. The control circuit further includes a second delay circuit having a second plurality of delay elements electrically connected at least in part in series. The second delay circuit is configured to generate a second control voltage associated with a second delay time. A first group of delay elements within the second plurality of delay elements exhibits the first delay time based on the first control voltage, and a second group of the second plurality of delay elements exhibits a second delay time based at least in part on the second control voltage.