Time-to-Digital Conversion Circuit With Randomized Start Phase

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Solution Overview

Problem

Existing time-to-digital conversion (TDC) circuits face challenges in achieving both reduced power consumption and improved linearity, as they often compromise on one aspect at the expense of the other, leading to suboptimal performance.

Innovation Solution

The proposed TDC circuit incorporates a start phase signal generating circuit that outputs a pseudo-random or periodically varying signal, allowing the oscillator phase to be randomized, which helps mitigate delay variations and improve linearity while enabling power consumption reduction by controlling oscillation based on input signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the oscillator circuit operates continuously to maintain stable phase signals, then measurement precision is improved, but power consumption increases

Engineering Contradiction:
Improvetime measurement accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The oscillator circuit operates periodically rather than continuously. The control circuit enables the oscillator to oscillate only during the measurement period (when start signal is detected) and disables it during idle periods. This periodic operation maintains measurement precision when needed while significantly reducing average power consumption during idle states.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The control circuit automatically detects the start signal and autonomously enables the oscillator, then detects the stop signal and autonomously disables it. This self-service mechanism eliminates the need for continuous external control while ensuring the oscillator operates only when measurement is required, optimizing both precision and power efficiency.

Inventive Principle:
Principle #25Self-service

2Device complexity

If fixed phase signals are used in the oscillator circuit, then circuit simplicity is maintained, but linearity deteriorates due to delay variations

Engineering Contradiction:
Improvecircuit configuration simplicityVSAvoidlinearity
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The oscillator circuit transitions from a static fixed-phase configuration to a dynamic variable-phase configuration. The phase of the oscillation signal is varied according to pseudo-random or periodically varying control signals, allowing the system to adapt and compensate for delay variations dynamically while maintaining relatively simple circuit architecture.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The phase parameter of the oscillator output is changed dynamically using control signals that vary pseudo-randomly or periodically. This parameter change allows the system to sweep through different phase values, thereby averaging out or compensating for fixed delay variations in the measurement path, improving linearity without requiring complex circuit restructuring.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If the oscillator phase is randomized using pseudo-random signals, then linearity is improved by mitigating delay variations, but device complexity increases

Engineering Contradiction:
ImprovelinearityVSAvoidcircuit configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The control circuit that generates pseudo-random or periodic phase modulation signals also serves to enable/disable the oscillator based on start/stop signals. This multi-functionality allows a single control block to handle both phase randomization for linearity improvement and power management, reducing overall device complexity despite the added phase modulation capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10895849B2Time-to-digital conversion circuit
Publication Date: 2021.01.19 SHARP KK
  • US10895849B2 patent drawing
  • US10895849B2 patent drawing
  • US10895849B2 patent drawing

AI summary

A time-to-digital conversion circuit includes; an oscillator circuit that outputs a plurality of phase signals different from each other, a counter that counts a number of edges of at least one phase signal among the plurality of phase signals and outputs a count signal, a phase sampling circuit that samples the value of each of the plurality of phase signals at a stop time point and outputs a stop phase signal, a start phase signal generating circuit that outputs a start phase signal, and an output circuit that, based on the count signal, the stop phase signal, and the start phase signal, generates an output signal, the output signal being a digital signal indicating a time period from a start time point to a stop time point.