TDC-Based Sampling Clock Correction for Phase Noise Jitter
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Solution Overview
Problem
Existing systems face challenges in reducing phase noise in clock signals for radio receivers, leading to increased power consumption and inadequate phase noise performance, which affects the fidelity of demodulated signals and increases error vector magnitude due to timing jitter.
Innovation Solution
The implementation of a time-to-digital converter (TDC) and phase noise measurement unit to measure the phase delay between oscillator and PLL clock signals, allowing for the generation of a phase noise signal that can be used to correct the sampling clock and reduce jitter, thereby improving signal fidelity without substantial increases in power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL-based phase noise reduction is used, then phase noise performance is improved, but power consumption increases substantially
Solution Approach 1:
The patent extracts only the essential phase noise measurement functionality from a full PLL system, implementing a simplified phase detector and TDC that measures phase noise without the overhead of complete PLL operation. This selective extraction achieves adequate phase noise performance while dramatically reducing power consumption.
Solution Approach 2:
The system performs partial phase noise measurement and correction only when needed, rather than continuously operating a full PLL. The phase noise correction is applied selectively to the sampling clock, providing sufficient correction without the excessive power consumption of continuous PLL operation.
2Measurement precision
If PLL bandwidth is increased to reduce phase noise, then phase noise attenuation is improved, but timing jitter increases
Solution Approach 1:
The system performs preliminary measurement of phase noise characteristics using the TDC, then applies correction based on these measurements. This preliminary measurement approach allows for optimized correction that reduces phase noise without introducing the timing jitter that would result from aggressive PLL bandwidth increases.
3Speed
If sampling rate is increased to improve signal fidelity, then signal resolution is improved, but phase noise impact increases
Solution Approach 1:
The system implements feedback by measuring phase noise with the TDC and using this measurement to correct the sampling clock phase. This feedback mechanism allows high sampling rates to be maintained while phase noise is continuously corrected, preserving signal fidelity without sacrificing sampling speed.
Data Source
AI summary
Phase noise in a first clock signal is measured using a time to digital converter (TDC) by determining variations in the phase delay between the first clock signal and a second clock signal. The TDC can include first and second series interconnections of delay elements, first and second sets of latches, and processing circuitry coupled to the latches and configured to determine the phase delay. The TDC can include a series interconnection of delay elements, latches, and circuitry configured to selectively adjust the control signal connected to the delay elements based on the output of the latches. The phase noise measurement can be used in a sampling circuit, so as to produce a second data signal from a first data signal based on the first clock signal and the measured phase noise.