TDC Circuit Self-Testing via D Flip-Flop AND Gate
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Solution Overview
Problem
Time-to-digital converter (TDC) circuits in time-of-flight (ToF) imagers require a simple and accurate self-testing method with low power consumption without degrading ranging performance.
Innovation Solution
A TDC circuit with self-testing functionality, incorporating a D flip-flop and AND gate configuration, where the D flip-flop is controlled by an enable signal and test signal, allowing for precise control during both normal and self-test modes, utilizing multi-phase clock signals to maintain performance while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used for TDC circuits, then testing accuracy can be maintained, but power consumption increases and ranging performance may be degraded
Solution Approach 1:
The TDC circuit performs self-testing using its own internal components and signals. The test signal is generated within the circuit itself and applied to the D flip-flop through the AND gate, allowing the circuit to test its functionality without requiring external testing equipment or additional power consumption that would degrade ranging performance.
Solution Approach 2:
The self-testing function is built into the circuit design beforehand, with the AND gate and control terminal configuration pre-established. This allows testing to be performed as part of the normal operation or during idle periods without requiring separate testing phases that would increase power consumption.
2Adaptability or versatility
If self-testing function is added to TDC circuit, then testing capability is improved, but device complexity increases
Solution Approach 1:
The existing D flip-flop and AND gate components are made multi-functional. The D flip-flop serves both its normal sampling function and the self-testing function by receiving test signals through the AND gate's control terminal. This eliminates the need for separate dedicated testing components, maintaining simplicity while adding versatility.
Solution Approach 2:
The self-testing functionality is merged with the existing sampling stage components. The AND gate combines the enable signal with the test signal to control the D flip-flop's sampling behavior, integrating testing capability into the normal operational path rather than adding a separate parallel testing path.
3Reliability
If self-testing function is implemented, then functional verification is improved, but power consumption during testing increases
Solution Approach 1:
The self-testing function can be activated periodically or during idle periods between normal ranging operations. The test signal is applied to the D flip-flop at specific time instants when the circuit is not actively performing ranging measurements, allowing functional verification without continuously increasing power consumption.
Solution Approach 2:
The AND gate acts as an intermediary that gates the test signal through the enable signal. This allows precise control over when testing occurs, enabling the circuit to test functionality only when needed and to limit testing duration, thereby minimizing additional power consumption while ensuring thorough functional verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient self-testing of TDC circuits with minimal power consumption and no degradation in ranging performance, ensuring proper functionality and reducing the risk of faulty operations.
Implementation Method 1
The sampling stage includes: first plurality of D flip-flops, wherein first input terminals of the first plurality of D flip-flops are configured to be coupled to a data signal, wherein first clock terminals of the first plurality of D flip-flops are configured to be coupled to respective ones of a plurality of clock signals
Implementation Method 2
an AND gate, wherein a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop
Implementation Method 3
the plurality of clock signals have a same frequency but different phases
Data Source
AI summary
A time-to-digital converter (TDC) circuit with self-testing function includes: a D flip-flop, where an input terminal of the D flip-flop is configured to be coupled to a data signal, and a clock terminal of the D flip-flop is configured to be coupled to a clock signal; and an AND gate, where a first input terminal of the AND gate is configured to be coupled to an enable signal of the TDC circuit, a second input terminal of the AND gate is configured to be coupled to a test signal, and an output terminal of the AND gate is coupled to a control terminal of the D flip-flop.