TDC-Based Serial Link Receiver for Low-Power Clock Alignment
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Solution Overview
Problem
Conventional low-power source-synchronous systems are limited by roundtrip propagation delay, leading to timing violations and errors, as they rely on phase interpolators for clock alignment, which consume substantial power and restrict data speeds to no greater than ½τ.
Innovation Solution
A receiver using a time-to-digital converter (TDC) measures unit interval and phase differences to align a delayed clock signal within the data eye, eliminating the need for phase interpolators and enabling high data rates while maintaining low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase interpolator is used for clock alignment, then clock signal can be aligned with data, but power consumption increases substantially
Solution Approach 1:
The patent removes the phase interpolator component from the system entirely. Instead of using a phase interpolator to align the clock signal with data, the invention uses a TDC-based measurement system that directly measures phase differences and uses programmable delay lines to achieve alignment, thereby eliminating the high power consumption associated with phase interpolators while maintaining clock alignment accuracy
Solution Approach 2:
The patent replaces the analog phase interpolation mechanism with a digital measurement and control system. The TDC converts analog phase differences into digital codes, which are then used to control programmable delay lines, substituting the continuous analog adjustment of phase interpolators with discrete digital control, resulting in lower power consumption
2Use of energy by moving object
If phase interpolator is eliminated for low power operation, then power consumption decreases, but data speed is limited to no greater than ½τ due to roundtrip propagation delay
Solution Approach 1:
The patent performs preliminary measurement of the roundtrip propagation delay using the TDC during an initialization or calibration phase. By measuring the actual delay τ and calculating the appropriate compensation value in advance, the system can set the programmable delay line to the correct setting before data transmission begins, enabling accurate sampling at higher data rates without requiring continuous phase interpolation during operation
Solution Approach 2:
The patent introduces a TDC-based measurement system and programmable delay line as intermediary components between the clock source and the data sampler. These intermediaries measure and compensate for propagation delay, allowing the system to overcome the conventional ½τ data rate limit by effectively extending the usable sampling window through precise delay adjustment
3Use of energy by moving object
If conventional low power serial link is used without phase interpolation, then power consumption is reduced, but timing violations and errors occur due to propagation delay
Solution Approach 1:
The patent implements a feedback mechanism where the TDC continuously or periodically measures the phase difference between the clock signal and the data signal. Based on these measurements, the system adjusts the programmable delay line setting to maintain optimal alignment, ensuring that timing accuracy is preserved even without the continuous operation of a phase interpolator, thus preventing timing violations and errors
Data Source
AI summary
A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.