DLL-Based Time-to-Digital Converter for Metastability-Safe Signal Alignment
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Solution Overview
Problem
Conventional LiDAR systems face challenges with high power consumption and limited sampling duration due to the use of Analog-to-Digital Converters (ADCs) and Time-to-Digital Converters (TDCs), which require high-speed sampling and lack accurate synchronization methods, leading to metastability issues when sampling asynchronous signals across different clock domains.
Innovation Solution
A TDC system incorporating a Delay Locked Loop (DLL) to generate multi-phase signals, a synchronizer to align the stop signal with the clock signal, and a time information calculator to determine the optimal sampling strategy based on the metastability state, ensuring accurate synchronization and reducing metastability errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ADC is used for high-speed sampling, then sampling speed is improved, but power consumption and area increase
Solution Approach 1:
The patent extracts the high-speed sampling function from the ADC and implements it separately using a TDC with counter and multi-phase clocks. The ADC is removed from the sampling path, keeping only the necessary time-to-digital conversion functionality, thereby reducing power consumption and area while maintaining high sampling speed capability.
Solution Approach 2:
The patent creates a functional copy of the sampling capability using TDC architecture with counter and multi-phase clocks, which replicates the high-speed sampling function without requiring the full ADC infrastructure, thus achieving similar performance with reduced resource consumption.
2Measurement precision
If TDC uses counter and multi-phase clocks for high resolution sampling, then measurement precision is improved, but sampling duration is limited
Solution Approach 1:
The patent performs preliminary synchronization of the stop signal with the clock signal using a synchronizer before the actual sampling operation. This preliminary alignment ensures that subsequent sampling operations can be performed accurately over extended periods without metastability issues, thereby extending the effective sampling duration while maintaining high resolution.
Solution Approach 2:
The patent implements a feedback mechanism where the synchronizer continuously monitors and adjusts the timing relationship between the stop signal and clock signal. This feedback loop ensures that synchronization is maintained throughout the sampling process, enabling long-duration high-resolution sampling by continuously correcting any timing drift or metastability conditions.
3Measurement precision
If sampling occurs close to clock edge, then time resolution is improved, but metastability errors increase
Solution Approach 1:
The patent introduces a synchronizer as an intermediary component between the asynchronous stop signal and the clock domain. This synchronizer acts as a mediator that prepares the stop signal for sampling by aligning it with the clock edges, enabling high time resolution sampling close to clock edges while preventing metastability errors through proper synchronization sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the synchronization of asynchronous signals in LiDAR systems, improving sampling resolution and reducing errors, allowing for more accurate distance measurements over longer durations while minimizing power consumption.
Implementation Method 1
a DLL (Delay Locked Loop) configured to delay a stop signal applied from an external element, and to output a multi-phase signal
Implementation Method 2
the synchronizer may determine whether the stop signal is detected at a DLL<N> channel or a DLL0> channel of the multi-phase signal outputted from the DLL. When the stop signal is detected at the DLL<N> channel or the DLL0> channel, the synchronizer may determine that the stop signal is present around an edge of the clock signal, and realign a rising edge of the stop signal with a falling edge of the clock signal
Implementation Method 3
a counter configured to output a counter value by using the synchronized stop signal applied from the synchronizer
Implementation Method 4
a time information calculator configured to calculate time information of the stop signal based on the counter value and the multi-phase signal
Data Source
AI summary
A TDC (Time-To-Digital Converter) includes: a DLL (Delay Locked Loop) to delay a stop signal applied from an external element and to output a multi-phase signal; a synchronizer to synchronize the stop signal with a clock signal by using the multi-phase signal, and to output a synchronized stop signal; a counter to output a counter value by using the synchronized stop signal applied from the synchronizer; and a time information calculator to calculate time information of the stop signal based on the counter value and the multi-phase signal.