Time-to-Digital Converter Stop Control for Low-Spur Phase Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing phase frequency detectors (PFDs) face challenges in accurately determining phase differences between clock signals due to injection locking effects, where a second oscillator can capture a first oscillator, leading to unstable phase locked loops (PLLs) and noise spurs in the output signal.

Innovation Solution

An electronic circuit with a timer circuit, selectively delayed transition generation circuitry, and phase determination circuitry that uses a pseudo-random binary sequence (PRBS) generator to randomize the stop signal selection, thereby whitening noise and improving phase delay measurement resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional PFD uses fixed stop signal selection, then the phase measurement process is simple, but noise spurs appear and phase measurement resolution is limited

Engineering Contradiction:
Improvephase measurement resolutionVSAvoidnoise spurs
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent applies dynamics by transitioning from fixed stop signal selection to dynamic random selection. A pseudo-random binary sequence (PRBS) generator randomly selects which stop signal (first or second) is generated based on the phase relationship between clock signals. This dynamic selection process whitenes noise and improves phase measurement resolution while reducing noise spurs in the output signal.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of stop signal selection from deterministic to probabilistic. By using a PRBS generator with adjustable characteristics (such as sequence length and randomization pattern), the system can optimize the balance between noise reduction and measurement accuracy. This parameter change enables flexible control over noise spur suppression while maintaining simple circuit implementation.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If randomization is applied to stop signal selection, then noise spurs are reduced and measurement resolution improves, but device complexity increases

Engineering Contradiction:
Improvephase measurement resolutionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a PRBS generator as an intermediary component between the phase detection logic and the stop signal selection mechanism. This intermediary randomly selects which stop signal to generate, effectively whitenening noise and reducing spurs. The PRBS generator adds minimal complexity compared to the overall PFD system while delivering significant noise reduction benefits.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs periodic randomization through the PRBS generator, which operates in a periodic manner to randomly select stop signals. This periodic action with pseudo-random patterns provides consistent noise whitening effects while maintaining predictable circuit behavior. The periodic nature of the PRBS sequence ensures stable performance without introducing additional complexity.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12170522B2Time-to-digital converter stop time control
Publication Date: 2024.12.17 TEXAS INSTRUMENTS INC
  • US12170522B2 patent drawing
  • US12170522B2 patent drawing
  • US12170522B2 patent drawing

AI summary

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.