Time-to-Digital Converter Stop Control for Low-Spur PLL Phase Sensing
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Solution Overview
Problem
Existing phase frequency detectors (PFDs) face challenges in accurately determining phase differences between clock signals due to injection locking effects and noise spurs caused by non-linearities in timing circuits, which affect the stability of phase locked loops (PLLs).
Innovation Solution
The proposed electronic circuit includes a timer circuit, selectively delayed transition generation circuitry, and phase determination circuitry that uses a pseudo-random binary sequence (PRBS) generator to randomize the stop signal selection, thereby whitening noise and improving phase measurement resolution by subtracting out additional delay from the timing result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional timer circuit is used to measure phase difference, then the circuit structure is simple, but noise spurs and non-linearities reduce measurement precision
Solution Approach 1:
The timer circuit is segmented into multiple delay stages, each contributing a known delay component. By dividing the timing measurement into discrete delay stages and using random selection of stop signals, the circuit achieves linear timing characteristics while maintaining manageable complexity through modular structure
Solution Approach 2:
A random number generator is introduced as an intermediary component that selects which delay stage output serves as the stop signal. This intermediary randomizes the measurement process to whiten noise and eliminate spurious tones, improving precision without requiring complete redesign of the timer circuit
2Stability of the object's composition
If deterministic stop signal timing is used, then the circuit operation is predictable, but noise spurs are generated that reduce stability
Solution Approach 1:
The system uses periodic clock signals to drive the delay stages and timer, maintaining regular operation. However, by randomly selecting which periodic cycle's output serves as the stop signal, the system converts deterministic periodic noise into randomized noise that appears as white noise rather than spurious tones
Solution Approach 2:
The random selection mechanism converts the harmful deterministic noise spurs into beneficial white noise. The randomness transforms correlated noise patterns into uncorrelated noise that can be filtered more effectively, improving overall system stability while using the same basic circuit components
3Measurement precision
If fixed delay stages are used in the timer, then the circuit is easy to manufacture, but non-linearities in delay components reduce measurement accuracy
Solution Approach 1:
The system changes the operational parameters by randomly selecting different delay stage combinations for each measurement. This parameter variation allows the circuit to average out non-linearities across multiple measurements, achieving higher accuracy without requiring each individual delay stage to be perfectly linear
Solution Approach 2:
Multiple delay stages are pre-configured with known delay values during manufacturing. The random selection process then combines these pre-configured stages in varying sequences, allowing the system to achieve linear timing characteristics through statistical averaging rather than requiring perfect linearity in each component
Data Source
AI summary
In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.