Time-to-Digital Converter Stop Delay Randomization for Phase Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing phase frequency detectors (PFDs) face challenges in accurately determining phase differences between clock signals due to injection locking effects, where a nearby oscillator can capture and synchronize with the reference oscillator, leading to phase noise and instability in phase locked loops (PLLs).
Innovation Solution
The proposed electronic circuit uses a timer circuit and phase determination circuitry with a selectively delayed transition of the second clock signal, generated through a multiplexer and pseudo-random binary sequence (PRBS) generator, to provide a digital time measurement of the phase difference, randomizing the stop signal delay to mitigate noise and improve resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a timer circuit is used to measure phase difference between clock signals, then measurement precision is improved, but phase noise increases due to injection locking effects from nearby oscillators
Solution Approach 1:
The patent applies preliminary action by generating a selectively delayed transition of the second clock signal before the phase measurement process. This pre-delayed signal is used to trigger the timer circuit, ensuring that the measurement starts with a known reference point that is already adjusted for expected delays, thereby reducing the impact of injection locking effects on measurement accuracy
Solution Approach 2:
The patent introduces an intermediary element in the form of a selectively delayed transition signal generated from the second clock signal. This intermediary signal acts as a mediator between the original clock signal and the timer circuit, allowing the system to measure phase differences while isolating the measurement process from direct injection locking effects of the original clock signals
2Device complexity
If the stop signal delay is fixed, then device complexity is reduced, but phase noise increases and measurement resolution decreases
Solution Approach 1:
The patent applies dynamics by making the stop signal delay variable rather than fixed. The delay is selectively adjusted based on random selection from multiple delay stages, allowing the system to adapt the delay parameter dynamically. This dynamic adjustment reduces phase noise and improves measurement resolution without requiring a completely complex circuit redesign
Solution Approach 2:
The patent changes the delay parameter of the stop signal by selecting from multiple predetermined delay stages. This parameter change approach allows the system to optimize measurement resolution by adjusting the delay value while maintaining a relatively simple circuit structure based on multiplexer selection among fixed delay stages
3Object-affected harmful factors
If multiple delay stages are used to randomize stop signal delay, then phase noise is reduced through whitening, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the delay function into multiple discrete delay stages, each providing a specific delay value. A multiplexer selects among these segmented delay stages based on random input, achieving noise whitening through statistical distribution of delay values while keeping each individual delay stage relatively simple in structure
Data Source
AI summary
In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.