Time-to-Digital Converter Stop-Time Randomization for PLL Phase Accuracy
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Solution Overview
Problem
Existing phase frequency detectors (PFDs) face challenges in accurately determining the phase difference between a clock signal and a reference clock signal, particularly due to noise and non-linearities introduced by delay elements in the timing measurement process.
Innovation Solution
The proposed electronic circuit includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. This circuit generates a phase difference measurement by calculating the elapsed time between a transition of the first clock signal and a selectively delayed transition of the second clock signal, while randomizing the stop time to mitigate noise effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a timer measures the elapsed time between clock signal transitions to determine phase difference, then phase measurement capability is provided, but noise and non-linearities from delay elements degrade measurement precision
Solution Approach 1:
The patent applies periodic action by using multiple delay stages that are periodically sampled and averaged. The delay elements are activated in a periodic sequence, and their outputs are combined through averaging to cancel out non-linearities and noise, thereby improving phase measurement precision while mitigating the harmful effects of individual delay element imperfections.
Solution Approach 2:
The patent implements feedback by measuring the phase difference using the timer and delay elements, then using this measurement to adjust and compensate for delays in subsequent measurements. The system continuously monitors the phase difference and uses this information to correct for non-linearities and noise in the delay elements, improving overall measurement accuracy.
2Measurement precision
If delay elements are used to create selectively delayed transitions for timing measurement, then phase difference determination is enabled, but non-linearities in delay elements reduce measurement accuracy
Solution Approach 1:
The patent uses periodic action by cycling through multiple delay stages in a regular sequence and averaging their outputs. This periodic sampling and averaging process compensates for non-linearities in individual delay elements, ensuring more consistent and accurate timing measurements while maintaining the necessary delay functionality.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the delay stage selection based on the measured phase difference. The system changes which delay elements are activated and how their outputs are weighted, optimizing the measurement process and compensating for non-linearities by varying operational parameters rather than relying on fixed delay characteristics.
Data Source
AI summary
In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.