TDC Supplement Circuit for High-Ratio Clock Phase Detection
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Solution Overview
Problem
Existing time-to-digital systems in frequency synthesizers face challenges in reducing hardware complexity, power consumption, suppressing supply interference, and enhancing linearity, particularly due to the high frequency difference between reference and variable clocks, which affects the performance and power efficiency of time-to-digital converters (TDCs).
Innovation Solution
A supplement circuit is introduced to generate a delayed reference clock signal and filtered pulses, using a filter window mechanism to suppress redundant pulses of the variable clock, thereby improving the performance and power efficiency of TDCs by dynamically adjusting the pulse width of the filter window in response to frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the TDC receives all pulses of the variable clock for phase detection, then the measurement precision is maintained, but the power consumption increases and supply interference worsens
Solution Approach 1:
The supplement circuit extracts and removes redundant pulses from the variable clock signal before it reaches the TDC. By taking out only the necessary pulse information for phase detection and filtering out excess pulses, the system maintains measurement precision while reducing the number of pulses processed by the TDC, thereby lowering power consumption and suppressing supply interference.
2Measurement precision
If the TDC processes high-frequency variable clock pulses, then the measurement resolution is maintained, but the device complexity increases
Solution Approach 1:
The supplement circuit acts as an intermediary between the variable clock source and the TDC. It pre-processes the high-frequency variable clock signal by generating delayed reference clock signals and filtering pulses, thereby simplifying the input signal to the TDC and reducing the complexity of the TDC circuit while maintaining time difference measurement resolution.
3Device complexity
If the filter window width is fixed, then the circuit complexity is reduced, but the adaptability to frequency changes deteriorates
Solution Approach 1:
The filter window width is made dynamic rather than fixed. The supplement circuit adjusts the width of the filter window based on the frequency of the variable clock signal. When the variable clock frequency changes, the filter window width automatically adapts, allowing the system to maintain optimal performance across different frequency ranges without requiring complex reconfiguration circuits.
4Loss of information
If redundant pulses are transmitted to the TDC, then the complete signal information is preserved, but the supply interference increases
Solution Approach 1:
The supplement circuit extracts and removes redundant pulses that cause supply interference while preserving the essential phase information needed for accurate time difference measurement. By selectively filtering out excess pulses that contribute to supply noise, the system maintains signal information completeness for phase detection while significantly reducing supply interference.
Data Source
AI summary
A time-to-digital system and associated frequency synthesizer are provided. The time-to-digital system receives a reference clock and a variable clock. The time-to-digital system includes a supplement circuit and a time-to-digital converter (TDC). The supplement circuit generates a delayed reference clock signal and at least one pulse of a variable clock ahead of a transition of the delayed reference clock signal. The delayed reference clock signal is generated according to a delay control signal and the reference clock signal. The delay control signal is determined in response to transitions of the variable clock, and frequency of the variable clock is significantly higher than frequency of the reference clock signal. Being coupled to the supplement circuit, the TDC receives the delayed reference clock signal and the at least one pulse of the variable clock and accordingly produces a TDC signal.