Synchronized Time-to-Digital Converter for Low Flicker Noise
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Solution Overview
Problem
Existing time-to-digital converters (TDCs) face challenges in achieving low flicker noise, which limits their resolution and accuracy in applications requiring precise time difference measurements between clock signals.
Innovation Solution
A counter-based TDC circuit is designed with a logic gate, synchronization circuit, and ripple counter to determine the time difference between clock signals, utilizing a low flicker noise clock source and flip-flops to minimize noise, thereby improving resolution and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional TDC designs are used, then device complexity is reduced, but measurement precision deteriorates due to high flicker noise
Solution Approach 1:
The TDC circuit is segmented into distinct functional blocks: trigger circuits for each clock input, a logic gate for comparison, a synchronization circuit with flip-flops, and a counter. This segmentation allows each component to be optimized independently for low noise while maintaining overall circuit manageability and achieving high measurement precision.
Solution Approach 2:
A synchronization circuit using flip-flops is introduced as an intermediary between the logic gate output and the counter. This intermediary synchronizes the logic gate output signal to a third clock, reducing flicker noise before the signal reaches the counter, thereby improving measurement precision without significantly increasing complexity.
2Measurement precision
If higher resolution TDC is implemented, then measurement precision improves, but flicker noise increases
Solution Approach 1:
The synchronization circuit acts as a noise-filtering intermediary that synchronizes signals to a stable third clock before counting, effectively reducing flicker noise generation while enabling high-resolution measurements through accurate pulse counting.
Solution Approach 2:
The trigger circuits automatically generate synchronized trigger signals based on their respective clock inputs, and the logic gate self-adjusts its output based on the relative timing of incoming clocks, enabling high-resolution measurement without external noise compensation mechanisms.
3Measurement precision
If low flicker noise clock source is used, then measurement accuracy improves, but device complexity increases
Solution Approach 1:
The third clock used for synchronization is merged with the counting operation, serving dual purposes: synchronizing the logic gate output to reduce flicker noise and providing the counting clock signal. This integration achieves high measurement accuracy without proportionally increasing circuit complexity.
Solution Approach 2:
The synchronization circuit serves multiple functions: it reduces flicker noise from the logic gate output, synchronizes the signal to a stable clock reference, and provides a clean trigger signal to the counter. This multi-functionality achieves high measurement accuracy while minimizing additional circuit complexity.
Data Source
AI summary
A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.