Time-to-Digital Converter Calibration Using a Virtual PLL
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-to-digital converters in clock generators experience gain errors that increase noise and spurs in the output, due to mismatched gains between coarse and fine converters, which affects the accuracy of clock signals.
Innovation Solution
A calibration technique using a virtual phase-locked loop is implemented to generate a calibration signal that adjusts the gain of the fine time-to-digital converter to match the coarse converter's gain, reducing phase noise and spurs by averaging error signals over multiple clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a time-to-digital converter is used to generate digital signals from clock signals, then clock signal generation is achieved, but gain errors increase noise and spurs in the output
Solution Approach 1:
The patent implements a feedback mechanism where the digital output from the time-to-digital converter is fed back through a virtual phase-locked loop to generate an error signal. This error signal is then used to adjust and calibrate the converter, creating a closed-loop system that continuously reduces gain errors and minimizes noise and spurs in the output.
Solution Approach 2:
The patent replaces traditional mechanical or analog calibration mechanisms with a digital virtual phase-locked loop system. This digital substitution allows for more precise error detection and correction, effectively reducing gain errors without the limitations of physical calibration components.
2Measurement precision
If gain calibration is performed to reduce errors, then measurement precision improves, but device complexity increases
Solution Approach 1:
The virtual phase-locked loop serves multiple functions: it generates error signals for calibration, acts as a feedback mechanism, and performs signal processing. By making this single circuit multi-functional, the patent achieves precise gain calibration without proportionally increasing overall device complexity.
Solution Approach 2:
The patent introduces a virtual phase-locked loop as an intermediary calibration circuit that mediates between the time-to-digital converter and the final output. This intermediary component simplifies the calibration process by providing a systematic approach to error correction without requiring complex direct modifications to the converter itself.
Data Source
AI summary
A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.