TDD Clock Recovery Using CDR Circuit Without Crystal Oscillator
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional TDD communication apparatuses for human body communication increase cost and power consumption due to the use of additional crystal oscillators for clock synchronization and lack clock stabilization in the CDR circuit.
Innovation Solution
A TDD communication apparatus utilizing a Clock Recovery & Data Retiming (CDR) circuit to generate and stabilize clock signals for both transmitting and receiving frames without a crystal oscillator, employing a voltage control oscillator, phase detector, and low pass filter to control the clock signal generation and recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a crystal oscillator is added to generate clock signals for transmitter and receiver, then clock synchronization is achieved, but cost and power consumption increase
Solution Approach 1:
The patent merges the clock generation function into the CDR circuit by adding a voltage control oscillator that operates in two modes: recovery mode (using received signal) and reference mode (generating reference clock). This eliminates the need for separate crystal oscillators in both transmitter and receiver, reducing power consumption while maintaining clock synchronization through the shared CDR circuit.
Solution Approach 2:
The CDR circuit is designed to perform multiple functions: it recovers clocks from received signals during reception and generates reference clock signals during transmission. This multi-functional design replaces dedicated crystal oscillators, reducing overall system power consumption while maintaining reliable clock synchronization for both transmit and receive operations.
2Reliability
If a crystal oscillator is added to generate clock signals for transmitter and receiver, then clock synchronization is achieved, but cost increases
Solution Approach 1:
The patent merges the clock generation function into the CDR circuit by adding a voltage control oscillator that operates in two modes: recovery mode (using received signal) and reference mode (generating reference clock). This eliminates the need for separate crystal oscillators in both transmitter and receiver, reducing component count and cost while maintaining clock synchronization through the shared CDR circuit.
Solution Approach 2:
The CDR circuit is designed to perform multiple functions: it recovers clocks from received signals during reception and generates reference clock signals during transmission. This multi-functional design replaces dedicated crystal oscillators, reducing overall system cost while maintaining reliable clock synchronization for both transmit and receive operations.
3Device complexity
If only CDR circuit is used for clock recovery, then device complexity is reduced, but clock stabilization is insufficient
Solution Approach 1:
The voltage control oscillator dynamically switches between two operational modes based on system state: in reception mode, it locks to the received signal frequency through the phase detector and low-pass filter, providing stable clock recovery; in transmission mode, it generates a stable reference clock. This dynamic operation enables the CDR circuit to provide adequate clock stabilization without requiring additional crystal oscillators.
Solution Approach 2:
The CDR circuit uses feedback through the phase detector and low-pass filter to stabilize the voltage control oscillator's output. The phase detector compares the oscillator output with the received signal (in recovery mode) or maintains reference frequency (in reference mode), and the low-pass filter provides smoothed feedback control. This feedback mechanism ensures adequate clock stabilization while keeping device complexity low by utilizing existing CDR circuit components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables stable communication by removing the need for additional crystal oscillators, reducing power consumption and cost while ensuring clock stabilization through the CDR circuit.
Implementation Method 1
The CDR circuit may include a voltage control oscillator for generating a signal of a preset reference frequency under control of the control unit, and generating a signal of a variable frequency corresponding to an input control voltage
Implementation Method 2
The CDR circuit detects, through a phase detector, a phase difference between an output frequency of a variable oscillator, which has an oscillating frequency variable in response to a control signal input, and an input data signal of the variable oscillator
Implementation Method 3
The CDR circuit may include a voltage control oscillator for generating a signal of a preset reference frequency under control of the control unit, and generating a signal of a variable frequency corresponding to an input control voltage; a phase detector for detecting a phase difference of the receiving frame and the signal output from the voltage control oscillator; and a low pass filter for generating the control voltage in response to the phase difference detected in the phase detector
Data Source
AI summary
A Time Division Duplex (TDD) communication apparatus and an operation method thereof can provide operation clock signals in the transmission and reception of the TDD communication apparatus using a Clock Recovery & Data Retiming (CDR) circuit, thereby stabilizing an operation without any crystal oscillator and reducing the power consumption. In a transmission time interval, a transmitting frame is processed using a clock signal of a reference frequency generated from the CDR circuit. In a reception time interval, a receiving frame is processed using a clock signal recovered from the receiving frame by the CDR circuit.