TDD PA Gate Hold Circuit for Low-Loss Tx/Rx Switching
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Solution Overview
Problem
Existing TDD wireless communication systems face challenges in efficiently and cost-effectively switching between downlink and uplink operational modes due to high component costs, reduced system reliability, increased power consumption, and efficiency losses, primarily because of the need for high-isolation RF switches and incomplete transistor shutdown during mode transitions.
Innovation Solution
A circuit that removes the RF switch from the antenna port and places it in the uplink path before the low-noise amplifier, utilizing a sample-and-hold circuit with voltage generators and capacitors to control the LDMOS power amplifier's gate voltage, allowing complete shutdown within stringent time limits while maintaining thermal compensation and reducing quiescent current during reception phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an RF switch is placed at the antenna port to enable TDD mode switching, then the system can switch between Tx and Rx modes, but the component cost increases due to high-isolation requirements
Solution Approach 1:
The patent extracts the RF switch from the antenna port location and relocates it to the uplink path before the LNA. This extraction from the critical antenna interface removes the requirement for high-isolation switches, thereby reducing component costs while preserving mode switching functionality through the alternative placement in the uplink signal path
Solution Approach 2:
The patent introduces a circulator as an intermediary component at the antenna port. The circulator provides the necessary isolation between Tx and Rx paths without requiring a high-isolation RF switch at the antenna interface, thus mediating the mode switching function while using lower-cost components
2Adaptability or versatility
If an RF switch is placed after the power amplifier in the downlink path, then mode switching is enabled, but the downlink path efficiency decreases due to insertion loss
Solution Approach 1:
The patent extracts the RF switch from the downlink path after the power amplifier and relocates it to the uplink path. This removal from the downlink signal path eliminates the insertion loss that would have been introduced by the switch, thereby improving downlink efficiency while maintaining mode switching capability through the uplink path placement
3Reliability
If the power amplifier is kept on during reception to maintain thermal compensation, then thermal tracking is preserved, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by pre-charging a capacitor during the transmission phase through the embedded thermal tracking circuit. This stored charge is then used during the reception phase to maintain the gate-source voltage and quiescent current, enabling the LDMOS to remain in a low-power state while preserving thermal compensation functionality without continuous power consumption
Solution Approach 2:
The patent implements self-service through the embedded thermal tracking circuit that automatically maintains thermal compensation during reception using the previously stored capacitor charge. The system serves itself by utilizing its own stored energy and thermal characteristics to maintain stability without requiring continuous external power or active control during the reception phase
4Adaptability or versatility
If an RF switch is used to handle high power levels for mode switching, then Tx/Rx commutation is achieved, but system reliability decreases
Solution Approach 1:
The patent extracts the RF switch from the high-power downlink path and relocates it to the low-power uplink path before the LNA. This extraction from the high-power environment removes the reliability concerns associated with switches handling high power levels, while the switch continues to perform mode switching function in the lower-power uplink signal path
Solution Approach 2:
The patent introduces a circulator as an intermediary that handles the high power levels in the downlink path, protecting the RF switch from exposure to high power. The circulator mediates between the high-power PA output and the rest of the system, allowing the switch to operate in a lower-power environment while maintaining mode switching capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces component costs, improves system reliability by handling lower power levels, minimizes power consumption by turning off the RF FET during reception, and enhances overall system efficiency by eliminating the RF switch in the downlink path, ensuring compliance with 3GPP standards for mode switching latency.
Implementation Method 1
The circuit comprises: at least a field-effect transistor RF FET operatively connected to a power amplifier PA
Implementation Method 2
transistor manufactories have embedded a quiescent current thermal tracking circuit T (a small integrated LDMOS FET located close to the active power LDMOS) in latest RF power integrated circuits
Implementation Method 3
utilizing a sample-and-hold circuit with voltage generators and capacitors to control the LDMOS power amplifier's gate voltage
Data Source
AI summary
A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.