TDD RF Front-End Switching Circuit with Sample-and-Hold Gate Bias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing TDD wireless communication systems face challenges in efficiently and cost-effectively switching between downlink and uplink operational modes due to high component costs, reduced system reliability, increased power consumption, and efficiency losses, primarily because of the need for high-isolation RF switches and incomplete transistor shutdown during mode transitions.
Innovation Solution
A circuit that removes the RF switch from the antenna port and places it in the uplink path before the LNA, utilizing a sample-and-hold circuit with voltage generators and resistors to control the LDMOS transistor's gate voltage, allowing complete shutdown within stringent time limits while maintaining thermal compensation, thus reducing component costs, improving reliability, and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an RF switch is placed at the antenna port to enable Tx/Rx switching, then mode switching capability is achieved, but component cost increases due to high-isolation requirements
Solution Approach 1:
The invention extracts the RF switch from the antenna port location and relocates it to the uplink path before the LNA. This extraction from the critical antenna interface removes the requirement for high-isolation switches at the antenna port, thereby reducing component costs while maintaining the essential Tx/Rx switching capability through the relocated switch position.
Solution Approach 2:
The invention introduces a sample-and-hold circuit as an intermediary between the voltage generator and the LDMOS transistor gate. This intermediary circuit enables precise control of the gate voltage during mode transitions, allowing the LDMOS to be completely turned off during Rx slots. This complete transistor shutdown eliminates the need for high-isolation RF switching at the antenna port, as the isolation is achieved through the controlled transistor state rather than requiring a high-performance RF switch.
2Adaptability or versatility
If an RF switch is placed at the antenna port to enable Tx/Rx switching, then mode switching capability is achieved, but system reliability decreases due to high power levels
Solution Approach 1:
The RF switch is extracted from the antenna port where it would be exposed to high power levels during transmission. By relocating the switch to the uplink path before the LNA, the switch operates at significantly lower power levels, thereby improving system reliability while maintaining the necessary mode switching functionality.
3Adaptability or versatility
If an RF switch is placed at the antenna port to enable Tx/Rx switching, then mode switching capability is achieved, but power consumption increases due to incomplete transistor shutdown
Solution Approach 1:
The sample-and-hold circuit acts as an intermediary that precisely controls the LDMOS transistor gate voltage. During Rx time slots, this intermediary circuit maintains the gate at a voltage level that ensures complete transistor shutdown, eliminating quiescent current draw. The circuit achieves this by holding the gate voltage at an appropriate off-state level while still enabling rapid transitions back to Tx mode when needed.
Solution Approach 2:
The invention implements periodic control of the LDMOS transistor state synchronized with the TDD frame structure. The sample-and-hold circuit periodically updates the gate voltage according to the Tx/Rx slot timing, ensuring the transistor is completely off during Rx slots and properly biased during Tx slots. This periodic action enables complete power shutdown during reception while maintaining readiness for rapid transmission startup.
4Adaptability or versatility
If an RF switch is placed at the antenna port to enable Tx/Rx switching, then mode switching capability is achieved, but DL path efficiency decreases due to insertion loss
Solution Approach 1:
The RF switch is extracted from the downlink path at the antenna port, removing the source of insertion loss from the DL signal path. By relocating the switch to the uplink path before the LNA, the downlink signal path is freed from switch-induced losses, thereby improving DL path efficiency while the switch continues to provide necessary mode switching functionality in the uplink path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient and fast mode switching compliant with 3GPP standards, reducing power consumption, enhancing system reliability, and minimizing DL path losses, while maintaining thermal compensation and quiescent current stability.
Implementation Method 1
at least a field-effect transistor RF FET operatively connected to a power amplifier PA on the downlink path (DL) of a RF front-end apparatus
Implementation Method 2
transistor manufactories have embedded a quiescent current thermal tracking circuit T (a small integrated LDMOS FET located close to the active power LDMOS) in latest RF power integrated circuits
Implementation Method 3
equipped with embedded thermal tracking device for thermal compensation
Data Source
Figure 1~3
Figure 4~5
Figure 6~7
AI summary
The circuit (C) for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor (RF FET) operatively connected to a power amplifier (PA) on the downlink path (DL) of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator (VgsOFF) connected to a large-value first resistor (Rhold), a second voltage generator (VGate) connected to a second resistor (RGate), a large- value hold capacitor (Chold), and a sample-and-hold circuit configured to be switched between a reception (Rx) configuration, wherein the first voltage generator (VgsOFF) is connected to the gate (G) of the field- effect transistor (RF FET) and the large- value capacitor (Chold) is connected to the first voltage generator (VgsOFF) through the first resistor (Rhold), and a transmission (Tx) configuration, wherein the gate (G) of the field-effect transistor (RF FET) is connected to the hold capacitor (Chold) and the hold capacitor (Chold) is connected to the second voltage generator (VGate) through the second resistor (RGate).